Logic

Record setting III-V MOSFETs are reported. For the first time performance better than state-of-the-art HEMTs is demonstrated. For a MOSFET with 10 nm unstrained InAs surface channel and L g = 130 nm operating at 0.5 V, on-current as high as I on = 601 μA/μm (at fixed I off = 100 nA/μm) is achieved. This record performance is enabled by g m, ext = 2.72 mS/μm and S = 85 mV/dec, DIBL = 40 mV/V, resulting from breakthroughs in epitaxy and III-V/dielectric interface engineering. Measured mobility is 7100 cm 2 /V.s at n s = 6.7×10 12 cm -2 . Device simulations further elucidate the performance potential of III-V N-MOSFETs.

We demonstrate scaled, replacement gate high-k/metal gate p-channel Ge FinFETs integrated onto 300mm Si wafers for which the best device shows record peak g m, ext =2.7mS/μm (g m, int =3.3mS/μm), Q (≡g m, ext /SS sat ) = 32.4 and I on = 497μA/μm at I off = 100nA/μm, all at V ds = -0.5V. The high performance is a result of successful integration of <;110> oriented, highly scaled Ge fins on silicon substrates and of a low D it gate stack with capacitance equivalent thickness=8Å. This optimized gate stack supports the highest hole mobility ever reported at sub-10Å CET. Furthermore, Ge FinFETs in the present work outperform any other reported Ge devices by more than ~2.5× (g m /SS metric) and ~2× (I on /I off metric) at shortest gate lengths (down to 20nm) to the best of our knowledge.

The characteristics of Al2O3/InSb MOSCAPs processed with different postdeposition annealing (PDA) temperatures are investigated. X-ray photoelectron spectroscopy analysis shows a significant reduction of InSb-oxides after HCl plus trimethyl aluminum treatment and oxide deposition. Multifrequency capacitance-voltage (C–V) characteristics exhibit low-frequency and asymmetrical C–V behaviors, in which capacitance in the InSb conduction band side is lower than in the valence band side. The electrical properties of the MOSCAPs are sensitive to PDA temperature and degraded significantly at PDA temperature > 300 °C. This degradation is closely related to the diffusion of In, Sb into Al2O3 as indicated by transmission electron microscopy analyses.

In this work a drift-diffusion simulator is utilized to study the electrostatics of a cylindrical gate-all-around junctionless nanowire transistor. For carrier transport properties such as carrier scattering and velocity in channel, a full band Monte Carlo is adopted to simulate non-equilibrium and ballistic behaviors. Two major cases: different S/D extension schemes and channel doping effects are examined in this study. It is observed that S/D extension underlap can benefit short-channel control and carrier velocity. In addition, channel doping is found to play an import role to increase carrier injection velocity in the junctionless nanowire transistors.

Impact of quantum confinement on electron mobility and its stress responses for (100) and (110)-orientated single-gate (SG) and double-gate (DG) nMOSFETs is studied. Unstrained electron mobility in (110) DG nMOSFETs is found to be significantly higher than that of (110) SG devices. This paper discusses another physical explanation to the experimentally observed higher electron mobility in (110) FinFET sidewall channels as compared to that observed in planar (110) devices. It is also found that the electron mobility increases faster under uniaxial tensile stress for (110) devices than for (100) ones. The higher mobility in (110) DG devices is attributed to the lighter confinement effective mass of Δ4 valleys and the non-parabolicity of Δ2 valleys along the <;110> directions. With high enough tensile strain, DG nMOSFETs with (110) surface orientation are expected to outperform these on (100).

We demonstrate MOVPE-growth of InAs/AlAs0.16Sb0.84/GaSb and InAs/AlAs0.16Sb0.84/InAs heterostructures of excellent quality as observed by transmission electron microscopy and x-ray diffraction 2-theta-omega and rocking curve scans with full width at half maximum routinely below 100″. Key points regarding interface control for heteroepitaxial nucleation are reviewed and the choice of suitable precursors to minimize the incorporation of C and O are discussed.

The growth of heterostructures lattice matched to InAs(100) substrates for high mobility electronic devices has been investigated. The oxide removal process and homoepitaxial nucleation depends on the deposition parameters to avoid the formation of surface defects that can propagate through the structure during growth which can result in degraded device performance. The growth parameters for InAs homoepitaxy were found to be within an extremely narrow range when using As4 with a slight increase using As2. High structural quality lattice matched AlAsxSb1−x buffer layer was grown on InAs(100) substrates using a digital growth technique with the AlAs mole fraction adjusted by varying the incident As flux. Using the AlAsxSb1−x buffer layer, the transport properties of thin InAs channel layers were determined on conducting native substrates.

Narrow 〈110〉Si oriented trenches with high aspect ratio served as template to grow Ge on Si (001) substrate. Cross section high resolution transmission electron microscopy reveals a high crystalline quality relaxed Ge inside the trench with only a few structural defects in the vicinity of a well ordered misfit dislocation grid at the Ge/Si interface. These dislocations are formed along the 〈111〉Ge lattice planes and terminate in the first 20 nm of grown Ge. The high structural Ge quality is maintained both parallel and perpendicular to the trench as was confirmed by additional plan view and cross section inspections along the trench.

Measurements made on heavily doped n-channel accumulation-mode planar metal-oxide-semiconductor field-effect transistors (MOSFETs) reveal that the channel mobility can reach values significantly higher than the bulk mobility at the same doing level. This effect is attributed to a screening effect: in the accumulation channel, the high concentration of the majority carriers brings about an electrostatic screening effect that reduces impurity coulomb scattering. As a result, mobility values that can reach twice the value expected in the bulk material are observed in the accumulation channel.

We report an ultrashallow metallic source/drain (S/D) contact scheme for fully self-aligned III-V NMOS with specific contact resistivity and sheet resistance which, for the first time, demonstrate performance metrics that may be compatible with the ITRS R ext requirements for 12-nm technology generation device pitch. The record specific contact resistivity between the contact pad and metallic S/D of ρ c = 2.7 ·10 -9 Ω·cm 2 has been demonstrated for 10 nm undoped InAs channels by forming an ultrashallow crystalline ternary NiInAs phase with R sh = 97 Ω/sq for a junction depth of 7 nm. The junction depth of the S/D scheme is highly controllable and atomically abrupt.