Memory

This work presents the first experimental demonstration of a Complementary Gain Cell (CGC) memory utilizing an n-type oxide semiconductor transistor (OSFET) as the write transistor and a p-type OSFET as the read transistor. Complementary (n-p) polarities effectively mitigate capacitive coupling of gain cells utilizing voltage sensing. Atomic Layer Deposition (ALD) Indium Tungsten Oxide (IWO) for nFET and Physical Vapor Deposition (PVD) Tin Oxide (SnO) for pFET are utilized. The ALD IWO nFET has a positive Vth of ∼1.15 V and subthreshold slope (SS) of ∼80 mV/dec. The fabricated SnO pFET has an Ion/Ioff ratio >5e4. The CGC achieves a measured retention time of 10,000 seconds under a −0.5 V write word line (WWL) standby voltage and can mitigate the WL capacitive coupling issue. The use of both n-type and p-type OS transistors for the 2T gain cell enables the potential for multilayer monolithic 3D integrated memory, paving the way for future “chip city” developments.

STT-MRAM shows great promise for use in artificial intelligence (AI) edge devices due to its compact bitcell area and high endurance. However, it faces read challenges because of its low TMR and RP. Conventional sense amplifiers have limitations in optimizing read energy and robustness while providing flexibility to exploit neural-net error tolerance. This article explores the design challenges of conventional sense amplifiers and examines how device parameters (TMR and RP) impact read performances. A novel capacitive-coupling sense amplifier is introduced to offer a new design space for balancing read energy and robustness. Combining the exploitation of neural-net error tolerance with sense amplifier and device co-design, a Design-Technology-System Co-Optimization (DTSCO) approach demonstrates a read energy reduction of 27.1% to 45.3% with minimal inference accuracy degradation in edge AI applications

The rapid development of artificial intelligence in recent decades has been continuously driving new software and hardware advancements. High-dimensional matrix-vector multiplication (MVM) is a crucial component in signal processing and machine learning computations. To achieve MVM, the 2D crossbar array of memristors has been widely discussed and studied. In this work, a novel SOT-MRAM device structure with 10ns write speed and >100x scalable resistance and read current are demonstrated to address the persistent problems of the traditional 2D crossbar array, leveraging its read-write path separation nature.

Integrating STT-MRAM with low voltage 2-terminal selector is a promising approach to boost embedded memory integration density. This work presents a new low voltage 1-Selector/1-STT-MRAM (1S1R) device based on SiNGeCTe (SNGCT) chalcogenide threshold selector. Remarkable 1S1R device performance is demonstrated under voltage pulse operation. For the first time, 1e9 read disturb- free cycles are experimentally demonstrated in STT-MRAM-based 1S1R. Moreover, the new device proves low voltage, high speed, low write error rate (<9 ppm at 1.7 V/ 50 ns), along with excellent write endurance (>1M cycles).

We demonstrated an 8Kb SOT-MRAM array which achieves the highest field-free switching speed (1ns) never reported. The low transistor switching voltage (V SW ) 1.5V at switching current density (J SW ) 68MA/cm² is attributed to the unique tungsten-based cSOT channel material (SCM) which provides high spin-Hall angle (~0.6) and low resistivity (160μΩ-cm) with 400°C thermal budget. The 8Kb SOT-MRAM array also showed good read window and array yield thanks to the promising MTJ etching process. Excellent performances such as high retention ( >>10 years at RT) and high endurance 7e12 cycles are demonstrated as well.

Considering the improved performance of MTJs and access transistors for MRAM at low temperatures, we proposed a novel design for embedded Cold MRAM to boost the cell density to 5.3x of a conventional 6T-SRAM. Together with the CMOS operated at cryogenic conditions, they can provide a potential solution for the high demanding HPC applications.

We demonstrate the reliability and magnetic immunity of STT-MRAM embedded in 16nm FinFET CMOS process. The technology supports endurance cycles up to 105 for wide temperature range from -40°C to 125°C with low bit error rate and passes 106 cycles at the worst temperature case of -40°C. Data retention sustains three solder-reflow cycles and up to 10 years with less than 1ppm error rate at 234°C. Read disturb error rate is less than 10-20 per read. Magnetic immunity of standby and active mode can reach 550Oe for 10 years 1ppm error rate and 800Oe for 0.1ppm error rate per write at 125 °C, respectively.

As spin-orbit-torque magnetic random-access memory (SOT-MRAM) is gathering great interest as the next-generation low-power and high-speed on-chip cache memory applications, it is critical to analyze the magnetic tunnel junction (MTJ) properties needed to achieve sub-ns, and fJ write operation when integrated with CMOS access transistors. In this paper, a 2T-1MTJ cell-level modeling framework for in-plane type Y SOT-MRAM suggests that high spin Hall conductivity and moderate SOT material sheet resistance are preferred. We benchmark write energy and speed performances of type Y SOT cells based on various SOT materials experimentally reported in the literature, including heavy metals, topological insulators and semimetals. We then carry out detailed benchmarking of SOT material Pt, β-W, and BixSe(1-x) with different thickness and resistivity. We further discuss how our 2T-1MTJ model can be expanded to analyze other variations of SOT-MRAM, including perpendicular (type Z) and type X SOT-MRAM, two-terminal SOT-MRAM, as well as spin-transfer-torque (STT) and voltage-controlled magnetic anisotropy (VCMA)-assisted SOT-MRAM. This work will provide essential guidelines for SOT-MRAM materials, devices, and circuits research in the future.

We report our work on the optimization of W/CoFeB/MgO structures to fulfill perpendicular magnetic anisotropy (PMA) requirements in the production of SOT-MRAM. By optimizing the natural oxidization process of deposited Mg layer and introducing different dust layers at W/CoFeB and CoFeB/MgO interfaces, PMA of W/CoFeB/MgO structures can be enhanced by about 100%, which is much higher than that in Ta-based structures. The origin of this PMA enhancement was further confirmed by transmission electron microscopy investigations. The corresponding SOT switching efficiency and current-induced effective fields were also investigated.

We demonstrate high yield results from a solder-reflow-capable spin-transfer-torque MRAM embedded in 22nm ultra-low leakage (ULL) CMOS technology. The technology supports -40 to 150°C operation and data retention though six solder reflow cycles and far exceeding 10 years at 150°C. Ten year native magnetic field immunity is >1100 Oe at 25°C at the 1ppm bit upset level. A shield-in-package solution demonstrates <; 1ppm bit upset rates from a disc magnet providing 3.5 kOe disturb field exposure for ~80 hours at 25°C. Trading off reflow capability, using smaller CD magnetic tunnel junctions, higher performance is achieved, for example read signal development times of 6ns at 125°C and average write pulse times slightly over 30ns at -40°C in a 20Mb design.