Materials Requirements of High-Speed and Low-Power Spin-Orbit-Torque Magnetic Random-Access MemoryAs spin-orbit-torque magnetic random-access memory (SOT-MRAM) is gathering great interest as the next-generation low-power and high-speed on-chip cache memory applications, it is critical to analyze the magnetic tunnel junction (MTJ) properties needed to achieve sub-ns, and fJ write operation when integrated with CMOS access transistors. In this paper, a 2T-1MTJ cell-level modeling framework for in-plane type Y SOT-MRAM suggests that high spin Hall conductivity and moderate SOT material sheet resistance are preferred. We benchmark write energy and speed performances of type Y SOT cells based on various SOT materials experimentally reported in the literature, including heavy metals, topological insulators and semimetals. We then carry out detailed benchmarking of SOT material Pt, β-W, and BixSe(1-x) with different thickness and resistivity. We further discuss how our 2T-1MTJ model can be expanded to analyze other variations of SOT-MRAM, including perpendicular (type Z) and type X SOT-MRAM, two-terminal SOT-MRAM, as well as spin-transfer-torque (STT) and voltage-controlled magnetic anisotropy (VCMA)-assisted SOT-MRAM. This work will provide essential guidelines for SOT-MRAM materials, devices, and circuits research in the future.
Interfacial engineering of SOT-MRAM to modulate atomic diffusion and enable PMA stability >400 ◦CWe report our work on the optimization of W/CoFeB/MgO structures to fulfill perpendicular magnetic anisotropy (PMA) requirements in the production of SOT-MRAM. By optimizing the natural oxidization process of deposited Mg layer and introducing different dust layers at W/CoFeB and CoFeB/MgO interfaces, PMA of W/CoFeB/MgO structures can be enhanced by about 100%, which is much higher than that in Ta-based structures. The origin of this PMA enhancement was further confirmed by transmission electron microscopy investigations. The corresponding SOT switching efficiency and current-induced effective fields were also investigated.
22nm STT-MRAM for Reflow and Automotive Uses with High Yield, Reliability, and Magnetic Immunity and with Performance and Shielding OptionsWe demonstrate high yield results from a solder-reflow-capable spin-transfer-torque MRAM embedded in 22nm ultra-low leakage (ULL) CMOS technology. The technology supports -40 to 150°C operation and data retention though six solder reflow cycles and far exceeding 10 years at 150°C. Ten year native magnetic field immunity is >1100 Oe at 25°C at the 1ppm bit upset level. A shield-in-package solution demonstrates <; 1ppm bit upset rates from a disc magnet providing 3.5 kOe disturb field exposure for ~80 hours at 25°C. Trading off reflow capability, using smaller CD magnetic tunnel junctions, higher performance is achieved, for example read signal development times of 6ns at 125°C and average write pulse times slightly over 30ns at -40°C in a 20Mb design.
A 28nm Integrated True Random Number Generator Harvesting Entropy from MRAMThis paper presents an integrated True Random Number Generator (TRNG) based on the random switching behavior of Magnetic Tunnel Junctions (MTJs) under low write current. A complete TRNG is designed with minimal overhead to an existing embedded MRAM in 28nm CMOS. To the best of our knowledge, this is the first experimental study of this random process and the first TRNG implemented with commercial STT-MRAM technology. The prototype adds only 180μm 2 to a standard MRAM array for TRNG operation. It passes all NIST randomness tests across -25 to 100°C, while consuming 18pJ/bit with 66Mbps throughput at the nominal condition.
Recent Progress and Next Directions for Embedded MRAM TechnologyMRAM can play a variety of on-chip memory roles in advanced VLSI technology spanning from high retention, solder-reflow-capable non-volatile memory (NVM) to dense non-volatile or high retention working RAMs. This paper describes results for a solder-reflow-capable MRAM NVM and for extensions that trade off high retention against speed, power, and density.
Large and Robust Charge-to-Spin Conversion in Sputtered Weyl Semimetal WTex with Structural DisorderTopological insulators have recently shown great promise for ultralow-power spin-orbit torque (SOT) devices thanks to their large charge-to-spin conversion efficiency originating from the spin-momentum-locked surface states. Weyl semimetals, on the other hand, may be more desirable due to their spin-polarized surface as well as bulk states, robustness against magnetic and structural disorder, and higher electrical conductivity for integration in metallic magnetic tunnel junctions. Here, we report that sputtered WTex thin films exhibit local atomic and chemical structures of Weyl semimetal WTe2 and host massless Weyl fermions in the presence of structural disorder at low temperatures. Remarkably, we find superior spin Hall conductivity and charge-to-spin conversion efficiency in these sputtered WTex films compared with crystalline WTe2 flakes. Besides, the strength of unidirectional spin Hall magnetoresistance in annealed WTex/Mo/CoFeB heterostructure is up to 20 times larger than typical SOT/ferromagnet bilayers reported at room temperature. We further demonstrate room temperature field-free magnetization switching at a current density as low as 0.97 MA/cm2. These large charge-to-spin conversion properties that are robust in the presence of structural disorder and thermal annealing pave the way for industrial production of Weyl semimetals. Our results open up a new class of sputtered Weyl semimetals for memory and computing based on magnetic tunnel junctions as well as broader planar heterostructures containing SOT/ferromagnet interfaces.
Among the emerging non-volatile binary memories, spin-torque-transfer RAM (STT-MRAM), spin-oribit-torque RRAM (SOT MRAM), and voltage controlled MRAM (VC MRAM), are particularly attractive owing to their low-voltage operation, high speed and endurance properties, and advanced CMOS technology compatibility. TSMC has developed and offers STT-MRAM solutions to overcome scaling limitations of embedded Flash technologies. TSMC is actively exploring SOT-MRAM and VC-MRAM internally and in conjunction with external research laboratories, consortia, and academic partners. TSMC SOT-MRAM exploration is driven by high-speed (<2ns) binary memory solutions that can be significantly denser than conventional 6T-SRAM solutions while also being much more energy efficient.