Low Dimensional Material & Device

Transistor research team at TSMC is also exploring devices built on materials having intrinsically 2D or 1D carrier transport (low-dimensional transport). Transition metal dichalcogenides, graphene nanoribbons, and carbon nanotubes, among others, are being investigated theoretically and experimentally. TSMC research work is both internally conducted and/or in collaboration with our academic partners through joint development projects, or by active technical participation in leading research consortia or research institutes worldwide. Here we invite you to explore some of TSMC’s recent published work in these fields of active exploratory research.

The benefits of using 2D and 1D materials include high mobility at atomic thickness, excellent gate control, and potential applications for low-power and high-performance devices. Thus, transistor scaling may be extended. In a recent publication, we have successfully demonstrated the growth of wafer-scale h-Boron Nitride monolayer, which is able to efficiently protect the channel 2D semiconductors from process damages and the charge impurity scattering from adjacent dielectrics. 1D semiconducting carbon nanotubes, with processes compatible with the backend-of-line (BOEL) fabrication temperature (< 400 oC), are a potential component for achieving monolithic 3D ICs. The proof-of-concept monolithic integration of carbon nanotube transistors on our 28 nm CMOS technology wafers has also been demonstrated.

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  • Wafer-scale single-crystal hexagonal boron nitride monolayers on Cu (111)

    2020
    Ultrathin two-dimensional (2D) semiconducting layered materials offer great potential for extending Moore’s law of the number of transistors in an integrated circuit1. One key challenge with 2D semiconductors is to avoid the formation of charge scattering and trap sites from adjacent dielectrics. An insulating van der Waals layer of hexagonal boron nitride (hBN) provides an excellent interface dielectric, efficiently reducing charge scattering2,3. Recent studies have shown the growth of single-crystal hBN films on molten gold surfaces4 or bulk copper foils5. However, the use of molten gold is not favoured by industry, owing to its high cost, cross-contamination and potential issues of process control and scalability. Copper foils might be suitable for roll-to-roll processes, but are unlikely to be compatible with advanced microelectronic fabrication on wafers. Thus, a reliable way of growing single-crystal hBN films directly on wafers would contribute to the broad adoption of 2D layered materials in industry. Previous attempts to grow hBN monolayers on Cu (111) metals have failed to achieve mono-orientation, resulting in unwanted grain boundaries when the layers merge into films6,7. Growing single-crystal hBN on such high-symmetry surface planes as Cu (111)5,8 is widely believed to be impossible, even in theory. Nonetheless, here we report the successful epitaxial growth of single-crystal hBN monolayers on a Cu (111) thin film across a two-inch c-plane sapphire wafer. This surprising result is corroborated by our first-principles calculations, suggesting that the epitaxial growth is enhanced by lateral docking of hBN to Cu (111) steps, ensuring the mono-orientation of hBN monolayers. The obtained single-crystal hBN, incorporated as an interface layer between molybdenum disulfide and hafnium dioxide in a bottom-gate configuration, enhanced the electrical performance of transistors. This reliable approach to producing wafer-scale single-crystal hBN paves the way to future 2D electronics.
  • Monolithic Heterogeneous Integration of BEOL Power Gating Transistors of Carbon Nanotube Networks with FEOL Si Ring Oscillator Circuits

    2019
    High performance carbon nanotube (CNT) network transistors with on-resistance (R on ) of <; 250 Ω are successfully integrated as back-end-of-the-line (BEOL) power gating devices onto Si CMOS wafers manufactured using 28-nm process technology. When the power supply is connected through the BEOL CNT network header array, the front-end-of-the-line (FEOL) Si ring oscillators (ROs) achieve a similar quiescent current (I DDQ ) and have the comparable active power (P ACTIVE ) consumption under the same operation frequency as compared to the operation without the power gating CNT transistors. The fabrication of CNT devices in the BEOL is verified to cause no performance degradation in the underlying FEOL Si CMOS devices. This study has successfully demonstrated heterogeneous integration of advanced Si logic circuits with low-cost and high-mobility CNT transistors in the BEOL fabricated at low, BEOL-compatible temperatures (250 °C).
  • Demonstration of 40-nm Channel Length Top-gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology

    2019
    For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS 2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS 2 channels on SiO x /Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10 6 , a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).
  • How 2D semiconductors could extend Moore’s law

    2019
  • First Demonstration of 40-nm Channel Length Top-Gate WS2 pFET Using Channel Area-Selective CVD Growth Directly on SiOx/Si Substrate

    2019
    Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS 2 p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS 2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS 2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of ~106, a S.S. of ~97 mV/dec., and nearly zero DIBL.
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