Logic

Notable progress has been reported for n-type contacts to two-dimensional (2D) materials, either through doping or through careful choice of contact metals. Here, we report on p-type contact engineering via substitutional doping and alloying. We tune the dopant concentration from lightly to heavily doped WSe2. We demonstrate that bilayer (2L) transition metal dichalcogenide (TMD) alloy can reach degenerate doping density for WSe2. The degenerate doping plays a critical role in lowering contact resistance (Rc) to metal. Extracted Rc is ~98 Ω·μm for a sheet resistance (Rsh) of 4.5 kΩ/sq, independent of the gate voltage (Vg). Pd/alloy contacts show superior thermal stability when compared to typical semimetal contacts (Bi and Sb).

Amorphous oxide semiconductor field-effect transistors (AOSFETs) exemplify the trade-off between mobility, stability, and threshold voltage (VTH). In this work, a new 5-axes AOSFET evaluation framework for back-end-of-line (BEOL) integration is proposed, including (i) ID extracted at a fixed over-drive beyond VTH at 1 pA/um for performance, (ii) IOFF, (iii) VTH, (iv) subthreshold slope (SS) at 1V VDS for off-state behaviors, and (v) VTH shift under positive bias stress for stability. To break the trade-off between mobility and VTH, an oxide capping layer and post-capping anneal are used on back-gated W-doped In2O3 (IWO) FETs. The oxide capping and anneal demonstrate stoichiometry-independent positive VTH shift on 1% and 2% IWO channel FETs by 0.85V and 0.4V, respectively, while mobility increases from 18.5 to 26 cm2V-1s-1 for 1% IWO. The contact resistance is also lowered from 2185 Ω-µm to 967 Ω-µm, enabling ION increase by 1.42×. With the oxide capping and anneal, the stability under positive bias stress improves by 300 mV to -67 mV VTH shift. An enhancement-mode 1% IWO FET is shown at 55 nm LCH with positive VTH = 0.53V, low IOFF = 160 pA/µm, ID = 192 µA/µm at 1E13 cm-2 charge density, and ID = 50 µA/µm extracted at a fixed over-drive voltage beyond 1 pA/um at 1V VDS.

Carbon nanotubes (CNTs) show great promise as channel material for future highly scaled transistors due to their atomic-thin body, high carrier mobility, and high injection velocity for both electrons and holes. In this work, we achieve ID greater than 300μA/μm at +/-1V VDS (iso-performance) for both N-type and P-type MOSFETs with 100nm gate length (LG) on densely aligned CNT array by self-aligned extension doping with a barrier booster [1]. Our process only modifies the extension dopant and contact metal to alter the device polarity while maintaining iso-performance. We also present the first experimental validation of tunable doping strength, mobility loss minimization, and leakage reduction capabilities of the barrier booster method, studied for top-gate CNT N-type MOSFET in this paper. Using this method, we achieve the best performance to date for N-type MOSFET on densely aligned CNT array, with ID>200μA/μm and Imax/Imin exceeding 104 simultaneously at 1V VDS and 500nm LG. With future improvements to the dielectric interface quality and device scaling, the benefits of CNT CMOS technology may be fully realized.

Efficient digital circuits require CMOS transistors with well-matched threshold voltage (VTH). In this work, we demonstrate for the first time CMOS co-integration, and well-matched VTH showcased through inverters based two-dimensional (2D) materials with supply voltage (VDD) of 1 V. We compare the fabrication of these circuits using the same channel material with using dedicated N and P channel materials (hetero-channel). Both instances use monolayer 2D transition metal dichalcogenide. The hetero-channel inverters allow superior performance at a relevant VDD = 1 V: voltage gain exceeding 10 V/V, noise margin over 80%, low average static-power consumption ~ 7 pW, and a switching voltage (VM) ~ 0.5 V. While still far from Si performance, reaching these numbers simultaneously requires multiple step developments working well together for monolayer 2D materials in the co-integrated flow. Sensitivity of various electrical metrics to process steps is also discussed in the paper.

This report presents the first electrical demonstration of a stacked nanosheet (NS) FET with a monolayer MoS2 channel, utilizing a typical nanosheet release process prior to high-k metal gate deposition. We demonstrate the fabrication of flat, two-stacked nanosheets with a monolayer MoS2 channel and a conformal HfOX/TiN gate stack. The stacked nanosheets, with a width of 100 nm, exhibit good release behavior, allowing for an integration scheme that supports gate lengths of up to 250 nm. IMAX/IMIN ratios of ~1E5 and a subthreshold swing of ~220 mV/dec are reported. Additionally, for the first time, the integration of stacked two NS WSe2 and two NS MoS2 in the same structural FET is demonstrated using the NS release and high-k metal gate conformal deposition process. The two channel materials represent typical PMOS and NMOS 2D materials, respectively.

We report the first direct extraction of CNT MOS interface metrics normalized to CNT length or CNT surface area using statistical impedance modeling and analysis of lateral capacitors measured between 100 and 300 K. Direct Dit extraction from impedance is a crucial step towards high performance CNT MOSFETs and is enabled by (1) a statistical approach towards modeling of CNT impedance, (2) a capacitor architecture meeting the requirements for Dit extraction, and (3) the extension of impedance acquisition to below 1 fF. A rigorous model treatment of surface potential fluctuations s in depletion due to fixed charge and CNT diameter variations allows to reproduce C-V features, to elucidate the physics, and to reconcile SS obtained from I-V curves with impedance data by extending the standard SS equation. CNT midgap Dit normalized to CNT surface area of  71012 cm¬-2 eV-1 and increasing towards the band edge to above 51013 cm-2 eV-1, s standard deviation s  2.5 kT, and a midgap capture length of 0.01 nm are extracted. Preliminary process optimizations demonstrate a positive impact on the Dit vs E curve.

This work demonstrates the first nanosheet FET built on an array of dense aligned carbon nanotubes. In this device structure, the gate surrounds an aligned array of CNTs with ≈300CNT/μm . At a channel length of 70 nm the drive current exceeds 1mA/μm at -0.5 V V_DS with sub- V_T slope of 135 mV/dec, and an IMIN of 76nA/μm.R_C of 20.5Ω−μm is extracted by transmission line method. This is record-high performance for transistors with CNT channel. However, reducing D_IT and channel variability are necessary to enable energy-efficient CMOS applications.

2D transition metal dichalcogenides (TMDs) show promise for transistor scaling, but their on-scale performance had not been proven yet. This work demonstrates contact length (Lc) scaling while holding a low contact resistance (R C ) down to 11 nm. Channel length (L_CH) scaling shows I ON can increase down to at least 12 nm with low Rc. The very scaled (_CH =19 nm and _C=12 nm) Mos2 transistor with Sb-based metal contact has current density of ~1130 μA/μm at V_DS = 1 V, and a low R_C of ~ 190 Ω.μm. These scaled transistors, processed within a back-end-of-line (BEOL) thermal budget, do not exhibit subthreshold swing (S.S.) degradation or observable drain-induced barrier lowering (DIBL) down to L_CH=12nm.

In this work, high-quality p-type SnO material is developed by PVD deposition. Sub-l00 nm short channel p-SnO devices are first demonstrated with current density 1 0~20 µA/µm, Ion/Ioff over 10⁴ , SS ~0.4 V/dec and hole mobility~2 cm² /V s. The monolithic 3D integration with oxide transistors in BEOL benefits FPGA, reducing its chip area and leakage while causing trivial overhead to its performance.

We present dielectric barrier booster for remote extension doping in low-dimensional materials (LDMs), e.g., ID Carbon Nanotubes (CNTs) and 2D MoS 2 . In contrast to prior work, the key idea is to "e;engineer"e; the thickness of a barrier layer (t BAR ) between LDM and dopant layer, in conjunction with the dopant layer itself, to optimize various remote extension doping trade-offs (e.g., transport, leakage, doping strength, parasitic load). Understanding such trade-offs requires extensive Design-Technology Co-Optimization (DTCO), not explored in prior literature. We explore a large space of ~50,000 design points through DTCO and derive various insights, including: (a) Barrier booster is key to enabling up to 1.5× energy-delay product (EDP) benefits for CNT FET ring oscillators vs. no-barrier case, (b) Barrier booster optimization depends on the target objective function: EDP optimization favors small t BAR (to increase extension charge density) while delay optimization favors large t BAR (to improve transport properties), (c) Doping guidelines derived from DTCO are LDM-specific: for example, we project 1.9× and 4.6× EDP benefits for extension-doped (with barrier booster) CNTs and MoS 2 , respectively, vs. undoped FETs. However, if EDP-optimal parameters for MoS 2 are used for CNTs (or vice-versa), the resulting EDP benefits are <1%.