Logic

A leading edge 2nm CMOS platform technology (N2) has been developed and engineered for energy-efficient compute in AI, mobile and HPC applications. This industry-leading N2 logic technology features energy-efficient gate-all-around nanosheet (NS) transistors, middle-of-line and backend-of-line interconnects with densest SRAM macro of ~38Mb/mm2. N2 delivers a full node benefit from previous 3nm node [2] in offering 15% speed gain or 30% power reduction with >1.15x chip density increase. N2 platform technology, equipped a new Cu scalable-RDL (sRDL), flat passivation and TSVs, co-optimizes holistically with 3DFabricTM technology enabling system integration/ scaling for AI/mobile/HPC product designs. N2 successfully met wafer-level reliability requirements and passed 1000hrs HTOL qual with high yielding 256Mb HC/HD SRAM (~>90%), and logic test chip (>3B gates) consisting of CPU/GPU/ SoC blocks. Currently in risk production, N2 platform technology is scheduled for mass production in 2H’25. N2P, 5% speed enhanced version of N2 with full GDS compatibility, targets to complete qualification in 2025 and mass production in 2026.

This study presents the first functional advanced CFET inverter with an industry-leading 48nm gate pitch, exhibiting well-balanced voltage transfer characteristics up to 1.2 V. In this paper, we elaborate on the advancements in our nanosheet-based monolithic complementary field-effect transistor (mCFET) process architecture, which builds upon our previous work. Key developments include a vertical dipole patterning process for independent n/p threshold voltage tuning, a vertical metallized drain local interconnect for n/p epitaxy connection at the common drain, and backside middle-of-line contacts and interconnects that improve performance and increase design flexibility. A comprehensive evaluation of the electrical performance of the mCFET devices with different configurations validates the effectiveness of our integrated process architecture. The successful demonstration of fully operational mCFET inverters marks an important milestone in the pioneering of CFET technology, paving the way for future logic technology scaling and the advancement of power, performance, area, and cost (PPAC).

In this work, a systematic non-conductive stress (NCS) is applied to understand NCS acceleration lifetime model for circuit applications at off-state high drain bias. The study revealed that elevated NCS could led to a rise in off-state channel current (IDOFF) caused by reverse hot carrier injection, affecting potential standby leakage. The examination of NCS influence on device degradation and the exploration of lowering NCS effects by reducing ISOFF was conducted. A study on a wide voltage range NCS validated the ISOFF and VDG accelerated IDOFF degradation lifetime model. The defined reliability boundary based on application-specific mission profiles provides guidance on the "Design for Reliability" (DFR) workflow for optimizing circuit design to mitigate off-state reliability risks before multi-project-wafer verification.

This paper provides a history of transistor innovations extending up to the present time and a look into the future of CMOS logic technology requirements for long-term sustainable growth on system-level integration, performance, and energy-efficiency, focusing on beyond-silicon MOSFETs and heat management research challenges. Applied research aimed to identify a transistor family that can replace and support sustainable energy-efficiency, performance, and density beyond the foreseeable silicon-based CMOS scaling is of up most importance. Equally important is stepping up efforts to establish scalable energy-efficient CMOS compatible memory element solutions that can address the logic-embedded SRAM and DRAM memory space. Sustainable increases in device counts per chip will require commensurate innovations on heat spreading and management to support the multilayer stacking dimension.

Given the limited space and cooling capacity in dilution refrigerators, it is challenging to scale the number of qubits for a fault-tolerant quantum computer (QC). In this paper, we study a custom-scaled CMOS technology to overcome the constraints in the dilution refrigerators. With Cryo-Design/ Technology CoOptimization (Cryo-DTCO) in an advanced node, one can then reduce the control power from 26.8 mW/ qubit to 8.4 mW/ qubit (∼0.31×). Projections suggest this may be sufficient to enable error corrections via surface codes for fault-tolerant computing.

We demonstrated that FinFET CMOS logic technologies are capable of ~50% speed increase at constant operating power when operating at 77K, or 0.27× power reduction at constant speed. The benefits arise primarily from steeper SS, carrier transport enhancement, and lower interconnect resistances. Better reliability enables additional speed gain for single-thread computing to ~70%. To extract this benefit, gate work function engineering at the transistor level is necessary. And design technology co-optimization at system level can further bring additional benefits.

For the first time, multiple-Vt (multi-Vt) device options with Vt range> 250 mV are achieved in standard cells at dimensions beyond 7nm technology node. To overcome the common scaling challenges of potential device options such as FinFET and gate all-around (GAA) nanosheet transistor - gate length and cell height scaling, key enablers are identified, including novel, thin, and conformal work function metal (WFM) with enhanced patterning efficiency, high-k (HK) engineering, and precise WFM patterning boundary control. This work enables design flexibility for advanced CMOS technology beyond 7nm node with critical differentiators.

We report on Qualcomm® Snapdragon™ SDM855 mobile SoC and world's first commercial 5G platform using industry-leading 7nm FINFET technologies. SDM855 exhibits CPU performance gain over the previous generation thanks to a new design architecture enabled by dual poly pitch process integration. Low voltage operation and tight spread in power consumption has been achieved through process and design co-development, delivering a high performance and low power solution for both mobile and AI applications. Extending the 7nm technology with 2 nd -year process enhancement demonstrates up to 50mV CPU Vmin reduction without any change to design rules, which paves the road for an integrated 5G mobile platform with connectivity.

Growth of ultrathin semiconducting nanowires (NWs) and incorporation of dopants suitable for future CMOS scaling targets (diameter <20 nm) is a challenge. Limits on dopant incorporation in thin NWs have led to concerns about the suitability of these structures. In this work, the atomic structure of the thinnest InAs NWs ever reported, down to 7 nm diameter, is characterized using transmission electron microscopy (TEM) and atom probe tomography (APT). It is demonstrated that there is no fundamental limit of Sn incorporation into ultrathin InAs NWs. Additionally, the Sn distribution of the Au catalyst particle controlling the growth is characterized.