Transistor Structure

TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.

TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.

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  • How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology

    Given the limited space and cooling capacity in dilution refrigerators, it is challenging to scale the number of qubits for a fault-tolerant quantum computer (QC). In this paper, we study a custom-scaled CMOS technology to overcome the constraints in the dilution refrigerators. With Cryo-Design/ Technology CoOptimization (Cryo-DTCO) in an advanced node, one can then reduce the control power from 26.8 mW/ qubit to 8.4 mW/ qubit (∼0.31×). Projections suggest this may be sufficient to enable error corrections via surface codes for fault-tolerant computing.
  • Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs

    We demonstrated that FinFET CMOS logic technologies are capable of ~50% speed increase at constant operating power when operating at 77K, or 0.27× power reduction at constant speed. The benefits arise primarily from steeper SS, carrier transport enhancement, and lower interconnect resistances. Better reliability enables additional speed gain for single-thread computing to ~70%. To extract this benefit, gate work function engineering at the transistor level is necessary. And design technology co-optimization at system level can further bring additional benefits.
  • Enabling Multiple-Vt Device Scaling for CMOS Technology beyond 7nm Node

    For the first time, multiple-Vt (multi-Vt) device options with Vt range> 250 mV are achieved in standard cells at dimensions beyond 7nm technology node. To overcome the common scaling challenges of potential device options such as FinFET and gate all-around (GAA) nanosheet transistor - gate length and cell height scaling, key enablers are identified, including novel, thin, and conformal work function metal (WFM) with enhanced patterning efficiency, high-k (HK) engineering, and precise WFM patterning boundary control. This work enables design flexibility for advanced CMOS technology beyond 7nm node with critical differentiators.
  • 7nm Mobile SoC and 5G Platform Technology and Design Co-Development for PPA and Manufacturability

    We report on Qualcomm® Snapdragon™ SDM855 mobile SoC and world's first commercial 5G platform using industry-leading 7nm FINFET technologies. SDM855 exhibits CPU performance gain over the previous generation thanks to a new design architecture enabled by dual poly pitch process integration. Low voltage operation and tight spread in power consumption has been achieved through process and design co-development, delivering a high performance and low power solution for both mobile and AI applications. Extending the 7nm technology with 2 nd -year process enhancement demonstrates up to 50mV CPU Vmin reduction without any change to design rules, which paves the road for an integrated 5G mobile platform with connectivity.
  • Sn Incorporation in Ultra-Thin InAs Nanowires for Next-Generation Transistors characterized by Atom Probe Tomography

    Growth of ultrathin semiconducting nanowires (NWs) and incorporation of dopants suitable for future CMOS scaling targets (diameter <20 nm) is a challenge. Limits on dopant incorporation in thin NWs have led to concerns about the suitability of these structures. In this work, the atomic structure of the thinnest InAs NWs ever reported, down to 7 nm diameter, is characterized using transmission electron microscopy (TEM) and atom probe tomography (APT). It is demonstrated that there is no fundamental limit of Sn incorporation into ultrathin InAs NWs. Additionally, the Sn distribution of the Au catalyst particle controlling the growth is characterized.
  • Key Technology Enablers of Innovations in the AI and 5G Era

    The proliferation of AI and the deployment of 5G networks accelerate the transformation of our society into a highly connected world. Semiconductors are the indispensable elements in realizing all the product innovations. The progress and challenges of the state of art CMOS technology and advanced packaging, considered as critical pillars to continue the improvement of system functions, will be reviewed.
  • 5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021um2 SRAM cells for Mobile SoC and High Performance Computing Applications

    A leading edge 5nm CMOS platform technology has been defined and optimized for mobile and HPC applications. This industry-leading 5nm technology features, for the first time, full-fledged EUV, and high mobility channel (HMC) finFETs with densest 0.021μm 2 HD SRAM. This true 5nm CMOS platform technology is a full node scaling from our successful 7nm node [4] in offering ~1.84x logic density, 15% speed gain or 30% power reduction. The 5nm platform technology successfully passed qualification [3] with consistently high yielding 256Mb HD/HC SRAM, and large logic test chip consisting of CPU/GPU/SoC blocks. Currently in risk production, this true 5nm platform technology is on schedule for high volume production in 1H 2020.
  • A High-Performance InAs/GaSb Core-Shell Nanowire Line-Tunneling TFET: An Atomistic Mode-Space NEGF Study

    Using a tight-binding mode-space NEGF technique, we explore the essential physics, design and performance potential of the III-V core-shell (CS) nanowire (NW) heterojunction tunneling field-effect transistor (TFET). The CS TFET “line-tunneling” current increases significantly with the core diameter d C and outperforms the best III-V axial “point-tunneling” NW heterojunction TFET I ON by up to 6× for d C = 6.6 nm. Reaching such a high level of current at low supply voltage, however, requires and involves specific and sometime unanticipated optimizations and physics that are thoroughly investigated here. In spite of the commonly accepted view, we also show and explain the weak gate-length dependency observed for the line-tunneling current in a III-V TFET. We further investigate the effect of electron-phonon scattering and discrete dopant impurity band tails on optimized CS NW TFETs. Including those non-idealities, the CS-TFET inverter performance significantly outperforms that of the axial TFETs. The low-power (LP) V DD = 0.35V CS-inverter delay is comparable to that of the high-performance (HP) Si CMOS using V DD = 0.55, which shows promise for an LP TFET technology with HP speed.
  • An Unique Methodology to Estimate The Thermal Time Constant and Dynamic Self Heating Impact for Accurate Reliability Evaluation in Advanced FinFET Technologies

    The increasing impact of self-heating effect (SHE) in complex FinFET structure is a serious reliability concern. Although the evaluation of SHE has become extremely arduous; this work proposes an in-situ layout based experimental solution to find out the precise thermal time constant (T TH ) due to SHE on advanced FinFET devices, even with the application of very pragmatic `circuit-like' gate and drain input waveforms. Using this precise T TH , the accurate dynamic thermal profile is found out from SPICE simulations. Finally, the true degradations due to different reliability mechanisms are evaluated including SHE impact and successfully compared with measured FinFET silicon data.
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