Logic

The proliferation of AI and the deployment of 5G networks accelerate the transformation of our society into a highly connected world. Semiconductors are the indispensable elements in realizing all the product innovations. The progress and challenges of the state of art CMOS technology and advanced packaging, considered as critical pillars to continue the improvement of system functions, will be reviewed.

A leading edge 5nm CMOS platform technology has been defined and optimized for mobile and HPC applications. This industry-leading 5nm technology features, for the first time, full-fledged EUV, and high mobility channel (HMC) finFETs with densest 0.021μm 2 HD SRAM. This true 5nm CMOS platform technology is a full node scaling from our successful 7nm node [4] in offering ~1.84x logic density, 15% speed gain or 30% power reduction. The 5nm platform technology successfully passed qualification [3] with consistently high yielding 256Mb HD/HC SRAM, and large logic test chip consisting of CPU/GPU/SoC blocks. Currently in risk production, this true 5nm platform technology is on schedule for high volume production in 1H 2020.

Using a tight-binding mode-space NEGF technique, we explore the essential physics, design and performance potential of the III-V core-shell (CS) nanowire (NW) heterojunction tunneling field-effect transistor (TFET). The CS TFET “line-tunneling” current increases significantly with the core diameter d C and outperforms the best III-V axial “point-tunneling” NW heterojunction TFET I ON by up to 6× for d C = 6.6 nm. Reaching such a high level of current at low supply voltage, however, requires and involves specific and sometime unanticipated optimizations and physics that are thoroughly investigated here. In spite of the commonly accepted view, we also show and explain the weak gate-length dependency observed for the line-tunneling current in a III-V TFET. We further investigate the effect of electron-phonon scattering and discrete dopant impurity band tails on optimized CS NW TFETs. Including those non-idealities, the CS-TFET inverter performance significantly outperforms that of the axial TFETs. The low-power (LP) V DD = 0.35V CS-inverter delay is comparable to that of the high-performance (HP) Si CMOS using V DD = 0.55, which shows promise for an LP TFET technology with HP speed.

The increasing impact of self-heating effect (SHE) in complex FinFET structure is a serious reliability concern. Although the evaluation of SHE has become extremely arduous; this work proposes an in-situ layout based experimental solution to find out the precise thermal time constant (T TH ) due to SHE on advanced FinFET devices, even with the application of very pragmatic `circuit-like' gate and drain input waveforms. Using this precise T TH , the accurate dynamic thermal profile is found out from SPICE simulations. Finally, the true degradations due to different reliability mechanisms are evaluated including SHE impact and successfully compared with measured FinFET silicon data.

A new wafer-level coupling plasma charge recorder fabricated with 7nm FinFET CMOS logic process is presented in this paper. This plasma ion charge recording device provides the historic and quantitative plasma ion charges of damascene metallization steps in advanced 7nm FinFET COMS logic processes. The high-resolution plasma ion recorder is formed by an accurate FinFET coupling structure to store the plasma ion level and distribution of the whole wafer. By a simple wafer-level WAT measurement, the promising plasma charge recording device can efficiently collect the accumulated ion charges, ion polarization, and tiny plasma fluctuation of each metallization process step in 7nm FinFET CMOS logic technologies, which definitely provides a superior device and method in developing a reliable and non-latent plasma damage process for 7nm FinFET technology and beyond.

We demonstrated that the fundamental scaling challenges of carrier transport and device variability can be tackled by S/D epitaxy and HK/MG RPG optimizations on the leading-edge 7nm Si n FinFETs, paving the way for continuous scaling. Mitigations of S/D long-range Coulomb interactions and gate-corner work-function roll-up enhance IDSAT by 18% and 9% respectively at constant gate overdrive, translating to a 13% speed-power enhancement in the ring oscillator. These techniques show larger IDSAT enhancements than that of IDLIN. By using an improved characterization method, their unique transport characteristics are clarified.

The electrical characteristics of <110> n/p Ge nanowire transistors (NWTs) with the cross section of 6×6nm2 have been studied. The ION performance and the subthreshold swing are simulated by multi-subband Boltzmann transport equation and ballistic quantum transport solvers, respectively. The performance of <110> nGe NWTs is sensitive to the barrier height of interfacial layer due to highly-anisotropic Λ-valleys. The dimension-dependent k·p parameters based on tight-binding full band are used to address the strong confinement of pGe NWTs. Comparing to Si NWTs, the intrinsic ION is twice as high for both n/p Ge NWTs at 28nm channel length. As the channel length is scaled down, such ION benefit is maintained till the tunneling effect comes in and degrades the subthreshold swing.

InAs nanowires (NW) grown by MOCVD with diameter d as small as 10 nm and gate-all-around (GAA) MOSFETs with d = 12-15 nm are demonstrated. I on = 314 μA/μm, and S sat =68 mV/dec was achieved at V dd = 0.5 V (I off = 0.1 μA/μm). Highest g m measured is 2693 μS/μm. Device performance is enabled by small diameter and optimized high-k/InAs gate stack process. Device performance tradeoffs between g m , R on , and I min are discussed.

We report the first demonstration of InAs FinFETs with fin width W fin in the range 25-35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height H fin = 20 nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length L g = 1 μm, peak transconductance gm,peak = 1430 μS/μm is measured at V d = 0.5 V demonstrating that electron transport in InAs fins can match planar devices.

This work investigates the formation mechanism of stress memorization technique (SMT)-induced edge dislocations and stacking faults during solid-phase epitaxy regrowth (SPER) using molecular dynamics (MD) simulation. During the SPER process of a patterned amorphous Si under a high-tensile capping film, growth fronts along the (1 1 0) and (0 0 1) planes collapse to form 5- and 7-rings which trigger the Frankel partial dislocation in the {1 1 1} plane. In addition, the line defects of stacking faults along {1 1 1} plane are generated with two symmetric boundaries of atomic structures which are confirmed as micro-twin defects. The MD simulation results are validated using high-resolution transmission electron microscopy and inverse fast Fourier transform images. The strain distribution obtained from the atomic structure reveals that the stress field is mainly caused by Frankel partial dislocations and the minor stress effect from the micro-twin defects.