Tackling Fundamental Challenges of Carrier Transport and Device Variability in Advanced Si nFinFETs for 7nm Node and Beyond
We demonstrated that the fundamental scaling challenges of carrier transport and device variability can be tackled by S/D epitaxy and HK/MG RPG optimizations on the leading-edge 7nm Si n FinFETs, paving the way for continuous scaling. Mitigations of S/D long-range Coulomb interactions and gate-corner work-function roll-up enhance IDSAT by 18% and 9% respectively at constant gate overdrive, translating to a 13% speed-power enhancement in the ring oscillator. These techniques show larger IDSAT enhancements than that of IDLIN. By using an improved characterization method, their unique transport characteristics are clarified.
A simulation perspective: The potential and limitation of Ge GAA CMOS
The electrical characteristics of <110> n/p Ge nanowire transistors (NWTs) with the cross section of 6×6nm2 have been studied. The ION performance and the subthreshold swing are simulated by multi-subband Boltzmann transport equation and ballistic quantum transport solvers, respectively. The performance of <110> nGe NWTs is sensitive to the barrier height of interfacial layer due to highly-anisotropic Λ-valleys. The dimension-dependent k·p parameters based on tight-binding full band are used to address the strong confinement of pGe NWTs. Comparing to Si NWTs, the intrinsic ION is twice as high for both n/p Ge NWTs at 28nm channel length. As the channel length is scaled down, such ION benefit is maintained till the tunneling effect comes in and degrades the subthreshold swing.
InAs Nanowire GAA n-MOSFETs with 12-15 nm Diameter
InAs nanowires (NW) grown by MOCVD with diameter d as small as 10 nm and gate-all-around (GAA) MOSFETs with d = 12-15 nm are demonstrated. I on = 314 μA/μm, and S sat =68 mV/dec was achieved at V dd = 0.5 V (I off = 0.1 μA/μm). Highest g m measured is 2693 μS/μm. Device performance is enabled by small diameter and optimized high-k/InAs gate stack process. Device performance tradeoffs between g m , R on , and I min are discussed.
InAs FinFETs with Hfin = 20 nm fabricated using a top-down etch process
We report the first demonstration of InAs FinFETs with fin width W fin in the range 25-35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height H fin = 20 nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length L g = 1 μm, peak transconductance gm,peak = 1430 μS/μm is measured at V d = 0.5 V demonstrating that electron transport in InAs fins can match planar devices.
Formation of multiple dislocations in Si solid-phase epitaxy regrowth process using stress memorization technique
This work investigates the formation mechanism of stress memorization technique (SMT)-induced edge dislocations and stacking faults during solid-phase epitaxy regrowth (SPER) using molecular dynamics (MD) simulation. During the SPER process of a patterned amorphous Si under a high-tensile capping film, growth fronts along the (1 1 0) and (0 0 1) planes collapse to form 5- and 7-rings which trigger the Frankel partial dislocation in the {1 1 1} plane. In addition, the line defects of stacking faults along {1 1 1} plane are generated with two symmetric boundaries of atomic structures which are confirmed as micro-twin defects. The MD simulation results are validated using high-resolution transmission electron microscopy and inverse fast Fourier transform images. The strain distribution obtained from the atomic structure reveals that the stress field is mainly caused by Frankel partial dislocations and the minor stress effect from the micro-twin defects.
Impact of SMT-induced edge dislocation positions to NFET performance
This work highlights the impact of SMT-induced edge-dislocation positions in nFET device design. Based on experimental results and atomic transport simulation, dislocations with reduced proximity and depth would increase the amount of SFs and TDs which induce high parasitic resistance and high I boff leakage current together. Trade-off among strained mobility, parasitic resistance and I boff should be made for advanced device design.
Ab initio study of dipole-induced threshold voltage shift in HfO2/Al2O3/(100)Si
The ab initio work quantitatively explains the physical mechanism of threshold voltage shifts in n-type and p-type metal-oxide-semiconductor field-effect transistors with HfO 2 /Al 2 O 3 gate stack. In the study, the θ phase alumina has been chosen for better lattice matching of the (100) HfO 2 and (100) Si substrate. Using dipole correction method, the dominant dipole moment responsible for the threshold voltage shift has been identified at the interface of HfO 2 /Al 2 O 3 . Our HfO 2 /Al 2 O 3 atomic model shows the dipole moment decreases almost linearly as the alumina thickness decreases from four monolayers (13 Å) to one monolayer (3 Å). On account of the effects of capacitance and the dipole moment, our ab initio calculation quantitatively explains the trend and sensitivity of experimental threshold voltage shifts on n- and p-MOSFET's.
CMOS-Compatible GaN-on-Si Field-Effect Transistors for High Voltage Power Applications
CMOS-compatible 100/650 V enhancement-mode FETs and 650 V depletion-mode MISFETs are fabricated on 6-inch AlGaN/GaN-on-Si wafers. They show high breakdown voltage and low specific on-resistance with good wafer uniformity. The importance of epitaxial quality is figured out in a key industrial item: high-temperature-reverse-bias-stress-induced on-state drain curent degradation. Optimization of epitaxial layers shows significant improvement of device reliability.
Germanium p-Channel FinFET Fabricated by aspect ratio trapping
We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at V DS =-0.5 V, good short-channel effect control, and high transconductance (g m =1.2 mS/μm at V DS =-1 V and 1.05 mS/μm at V DS =-0.5 V for L G =70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.
Electrical Characterization and Materials Stability Analysis of La2O3/HfO2 Composite Oxides on n-In0.53Ga0.47As MOS Capacitors With Different Annealing Temperatures
In this letter, a high-k composite oxide composed of La 2 O 3 and HfO 2 is investigated for n-In 0.53 Ga 0.47 As metal-oxide-semiconductor (MOS) capacitor application. The composite oxide was formed by depositing five layers of La 2 O 3 (0.8 nm)/HfO 2 (0.8 nm) on InGaAs with post deposition annealing at 500°C. The MOS capacitors fabricated show good inversion behavior, high capacitance, low leakage current, with excellent interface trap density (D it ) of 7.0×10 11 cm -2 eV -1 , small hysteresis of 200 mV and low capacitance equivalent thickness of 2.2 nm at 1 kHz were also achieved.
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
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