Transistor Structure

TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.

TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.

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  • Electrostatics and ballistic transport studies in junctionless nanowire transistors

    In this work a drift-diffusion simulator is utilized to study the electrostatics of a cylindrical gate-all-around junctionless nanowire transistor. For carrier transport properties such as carrier scattering and velocity in channel, a full band Monte Carlo is adopted to simulate non-equilibrium and ballistic behaviors. Two major cases: different S/D extension schemes and channel doping effects are examined in this study. It is observed that S/D extension underlap can benefit short-channel control and carrier velocity. In addition, channel doping is found to play an import role to increase carrier injection velocity in the junctionless nanowire transistors.
  • Quantum confinement point of view for mobility and stress responses on (100) and (110) SingleGate and double-gate nMOSFETs

    Impact of quantum confinement on electron mobility and its stress responses for (100) and (110)-orientated single-gate (SG) and double-gate (DG) nMOSFETs is studied. Unstrained electron mobility in (110) DG nMOSFETs is found to be significantly higher than that of (110) SG devices. This paper discusses another physical explanation to the experimentally observed higher electron mobility in (110) FinFET sidewall channels as compared to that observed in planar (110) devices. It is also found that the electron mobility increases faster under uniaxial tensile stress for (110) devices than for (100) ones. The higher mobility in (110) DG devices is attributed to the lighter confinement effective mass of Δ4 valleys and the non-parabolicity of Δ2 valleys along the <;110> directions. With high enough tensile strain, DG nMOSFETs with (110) surface orientation are expected to outperform these on (100).
  • Mobility and screening effect in heavily doped accumulation-mode metal-oxide-semiconductor field-effect transistors

    Measurements made on heavily doped n-channel accumulation-mode planar metal-oxide-semiconductor field-effect transistors (MOSFETs) reveal that the channel mobility can reach values significantly higher than the bulk mobility at the same doing level. This effect is attributed to a screening effect: in the accumulation channel, the high concentration of the majority carriers brings about an electrostatic screening effect that reduces impurity coulomb scattering. As a result, mobility values that can reach twice the value expected in the bulk material are observed in the accumulation channel.
  • Molecular Dynamic simulation study of stress memorization in Si dislocations

    Stress-Memorization-Technique by Si dislocations is effective in enhancing NFET device performance [1,2]. For the first time, MD (Molecular Dynamic) simulations are applied to explain the formation mechanism of dislocations during the Solid-Phase-Epitaxy-Regrowth (SPER) process. A semi- empirical TCAD method based on lattice-KMC (L-KMC) is then developed to predict dislocation formation. The simulated dislocation positions agree well with silicon experiments characterized by TEM. TCAD simulations show that the resulting dislocations are along the [111] direction and provide ~650MPa average longitudinal stress in channel regions, consistent with Nano-Beam-Diffraction (NBD) strain measurement. The channel stress is predicted by simulation to further increase by 1.5X after the poly-silicon gate removal step in a replacement-gate process. The dislocation SMT enhances NFET electron mobility by 25% and Ion-Ioff performance by 15%.
  • 28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications

    An industry leading 28nm high-performance mobile SoC technology featuring metal-gate/high-k process is presented. The technology is optimized to offer wide power-to-performance transistor dynamic range and highest wired gate density with superior low-R/ELK interconnects, critical for next generation mobile computing/SOC applications. Through process and design optimization, historical trend is maintained for gate density and SRAM cell sizes. Variations control strategy through process and design collaboration is also described.
  • Integrated stress and process calibration in strained-si devices

    We present a novel calibration methodology that (i) integrates dopant diffusion, mechanical strain and bandgap narrowing for accurate device short channel effect modeling and (ii) deploys stress dependent mobility model for robust device performance projection especially on effective drive current (Ideff). Good agreement is obtained between the model calibration and experimental measurements over the full gate length range examined. Moreover, a general mobility gain with respect to uniaxial stress is presented.
  • Series resistance and mobility extraction method in nanoscale MOSFETs

    This paper presents a BSIM-based method for source/drain series resistance and mobility extraction in nanoscale strained-silicon metal oxide semiconductor field effect transistors (MOSFETs) with halo implants. This method is more accurate than the conventional channel-resistance and shift and ratio method because it considers the gate-length dependence of mobility caused by local uniaxial stress and laterally nonuniform channel doping. We have verified this method using samples with different stressor/doping conditions and good agreement with experimental data has been obtained. The accuracy of the Berkeley Short-channel IGFET model (BSIM) extraction method is also proven by simulated current–voltage characteristics with different external resistant values. Significant mobility degradation in the short-channel regime has been observed for various uniaxial stressors. This method may serve as a suitable process monitor tool for ultrashallow junction and strained process development.
  • A millisecond-anneal-assisted selective fully silicided (FUSI) gate process

    We demonstrate, for the first time, an integration-friendly selective PMOSFET fully silicided (FUSI) gate process. In this process, a millisecond-anneal (MSA) technique is utilized for the nickel silicide phase transformation. A highly tensile FUSI gate electrode is created and hence exerts compressive stress in the underlying channel. The highly flexible integration scheme successfully, and exclusively, implements uniform P + FUSI gates for PMOSFETs while preserving a FUSI-free N + poly-Si gate for NMOSFETs with the feature size down to 30 nm. A 20% improvement in FUSI- gated PMOSFET I on - I off is measured, which can be attributed to the enhanced hole mobility and the elimination of P + poly-gate depletion.
  • 32nm gate-first high-k/metal-gate technology for high performance low power Applications

    A 32 nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 muA/mum (n/p) are achieved at I off =100 nA/mum, V dd =1 V, 30 nm physical gate length and 130 nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of 1020/700 muA/mum (n/p) at total I off ~1 nA/mum @ V dd = 1V. Low sub-threshold leakage was achieved while successfully containing I boff and I goff well below 1 nA/um. Ultra high density 0.15 um 2 SRAM cell is fabricated by high NA 193 nm immersion lithography. Functional 2 Mb SRAM test-chip in 32 nm design rule has been demonstrated with a controllable manufacturing window.
  • Modeling and characterization of advanced phosphorus ultra shallow junction using germanium and carbon coimplants

    A continuum model of phosphorus diffusion with germanium and carbon coimplant has been proposed and calibrated based on secondary ion mass spectroscopy (SIMS) profiles aiming at ultra shallow junction (USJ) formation in advanced CMOS technologies. The phosphorus diffusion behaviors are well captured by our model under various implant and annealing conditions, representing a significant step towards advanced n-type USJ formation technique using phosphorus and carbon coimplant for aggressively scaled CMOS technologies.
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