Memory

For the first time, we demonstrate a transition metal dichalcogenide (TMD) Ferroelectric Field-Effect Transistor (FeFET) with ultra-high endurance (>10¹² measured) and retention time exceeding 10 years. The devices consist of an ultrathin Hf-Zr-based (HZO) ferroelectric deposited by ALD on a stack of AlO x /MoS 2 with process temperature <250°C. By using a 2.5nm HZO layer and a monolayer (1L) MoS 2 , a record-low operating voltage < 1V is reported thanks to excellent gate control. The device fabrication is compatible with Back-End-of-Line (BEoL) processes in advanced CMOS technologies. Array-level projections show that a sufficient memory window is maintained at a supply voltage (V DD ) of IV. This device has promise for high-density memory embedded in scaled CMOS technology nodes.

We propose a new approach where internal distributed variables of ferroelectric FETs (FEFET) are directly extracted from measured positive-up negative-down (PUND) FEFET and ferroelectric capacitor (FECAP) P-V data. Quantitative energy band diagrams (EBDs) reveal the detailed device physics by providing internal device quantities including potential, polarization, carrier density, and defect density in energy and real space at each external bias point. The insights into internal device quantities shed light onto the intricate symbiosis between polarization switching and charge emission/capture, stress induced memory window closure due to permanently trapped charge and/or interface/channel defect generation; and phenomena including read delay after write, polarization switching, and polarization walkout/snapback. The new key findings provide a path into possible solutions of performance and lifetime limitations of both Si and oxide channel FEFETs.

After 10¹¹ high endurance cycles with memory window (MW) =0.9 V is achieved for the 3D gate-all-around (GAA) nanosheet (NS) ferroelectric field-effect transistor (FeFET) based on double-HZO; the aim is to homogenize the corner field and mitigate dead zones. The interlayer Al 2 O 3 or TiN in the double-HZO exhibits MW enhancement or low access voltage, respectively. The proposed MFMFS GAA-FeFET demonstrates a low V P/E = ±3.5 V (±2.3 MV/cm), large MW = 1.3 V, >10¹¹ robust endurance cycles, and stable storage with data retention of >2×10⁴ s; therefore, physical dimension scaling of the embedded nonvolatile memory (eNVM) is feasible for future generations.

For the first time, we demonstrate Ferroelectric Tunneling Junctions (FTJs) with both (a) 10-year retention time projected from measured data and (b) robust endurance (> 10⁸ cycles) with the on-off ratio >10× by inserting a 1.8nm Al 2 O 3 interfacial layer (IL) into the FTJs. Compared with Metal-Ferroelectric-Metal (MFM) FTJs, higher orthorhombic phase (~6×) was verified by physical analyses and first-principles calculations in our proposed Metal-Ferroelectric-IL-Metal (MFIM) FTJs, resulting in the remanent polarization (2P r ) which improves the retention and the on-off ratio significantly.

In this study, polarization fatigue of HfZrO ferroelectric is investigated with SILC (stress-induced-leakage-current) measurement under different E-field stresses. Under high-field, we observed strong correlation between polarization wake-up and SILC increase. This is attributed to oxygen vacancy redistribution and percolation path formation, especially at high frequency cycling. However, polarization fatigue at low field is found to occur without SILC increase. P-E loop measurements revealed that charge trapping is the main contributor under the low-bias. We demonstrated that the fatigue caused by low-field stress could be effectively recovered through an interspersed periodical, short-term cycles at high-field to manage charge trapping and oxygen vacancy redistribution, thus resulting in prolonged endurance to >1E12 cycles without SILC degradation at room temperature. We also validated that a negligible fatigue switching in HfZrO can be achieved at -40°C as low-temperature operation further reduces charge trapping.