Memory

Memory

Data is the most valuable resource in today’s digital economy. Currently over 2.5 quintillion (1018) bytes of data are generated daily and the pace is accelerating. More data than ever needs to be processed. Memory plays a key role in the flow of data. The gap between logic and memory is a bottle neck to system performance. To optimize the trade-off between cost and performance, a hierarchical memory system has been adopted. At the top of the hierarchy are static random access memories (SRAM) and dynamic random access memory (DRAM), both inherently volatile. SRAM is integrated right on the logic chips as cache memory to provide fastest access. DRAM is physically smaller than SRAM and consequently supports higher capacity. DRAM is generally an off-chip memory solution and ~10x slower than SRAM due to the need for constant refresh. Non-volatile memories (NVM) such as Flash are next in the hierarchy providing much higher memory capacity and density while also preserving information in the absence of power.

Recent new technologies are emerging rapidly to bring processing tasks near to or inside the memory to improve computing efficiency and enable new functionalities. Emerging NVMs use new types of materials and mechanisms to store data. They are promising for blending the memory hierarchy to boost the overall performance. Furthermore, their unique characteristics offer great potential to enable new applications (e.g. neuromorphic computing) and novel architectures (e.g. 3D integration).

TSMC’s non-volatile memory solutions include Flash, Spin-transfer torque magnetic random access memory (STT-MRAM), and resistive random access memory (RRAM). TSMC is also actively exploring phase change random access memory (PCRAM), and spin-orbit torque MRAM (SOT-MRAM) elements, as well as selector devices which are essential to support higher density cross-point array architectures.

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1-10 of 23
  • Direct Quantitative Extraction of Internal Variables from Measured PUND Characteristics Providing New Key Insights into Physics and Performance of Silicon and Oxide Channel Ferroelectric FETs

    2022
    We propose a new approach where internal distributed variables of ferroelectric FETs (FEFET) are directly extracted from measured positive-up negative-down (PUND) FEFET and ferroelectric capacitor (FECAP) P-V data. Quantitative energy band diagrams (EBDs) reveal the detailed device physics by providing internal device quantities including potential, polarization, carrier density, and defect density in energy and real space at each external bias point. The insights into internal device quantities shed light onto the intricate symbiosis between polarization switching and charge emission/capture, stress induced memory window closure due to permanently trapped charge and/or interface/channel defect generation; and phenomena including read delay after write, polarization switching, and polarization walkout/snapback. The new key findings provide a path into possible solutions of performance and lifetime limitations of both Si and oxide channel FEFETs.
  • Engineering defects in pristine amorphous chalcogenides for forming-free low voltage selectors

    2022
    Amorphous chalcogenide-based threshold selectors are among the most promising two-terminal technologies for high density non-volatile memories. However, the necessity of a high voltage forming operation makes their implementation in low voltage logic chips a key challenge. This work reports a new approach towards forming-free chalcogenide selectors, where extra defects are introduced to assist the forming process and reduce the forming voltage. The added defects are shown to increase the conductivity of the pristine chalcogenide and can be annihilated after the first switching pulse operation. Forming-free low voltage selectors based on SiNGeCTe (SNGCT) chalcogenide are demonstrated along with excellent endurance characteristics over 1010 cycles.
  • Endurance > 1011 Cycling of 3D GAA Nanosheet Ferroelectric FET with Stacked HfZrO2 to Homogenize Corner Field Toward Mitigate Dead Zone for High-Density eNVM

    2022
    After 1011 high endurance cycles with memory window (MW) =0.9 V is achieved for the 3D gate-all-around (GAA) nanosheet (NS) ferroelectric field-effect transistor (FeFET) based on double-HZO; the aim is to homogenize the corner field and mitigate dead zones. The interlayer Al 2 O 3 or TiN in the double-HZO exhibits MW enhancement or low access voltage, respectively. The proposed MFMFS GAA-FeFET demonstrates a low V P/E = ±3.5 V (±2.3 MV/cm), large MW = 1.3 V, >1011 robust endurance cycles, and stable storage with data retention of >2×104 s; therefore, physical dimension scaling of the embedded nonvolatile memory (eNVM) is feasible for future generations.
  • First Fire-free, Low-voltage (~1.2 V), and Low Off-current (~3 nA) SiOxTey Selectors

    2022
    Operating voltage compatibility and low power consumption are crucial for on-chip integration of high-density one-selector-one-resistor (1S/1R) arrays. However, traditional chalcogenide-based threshold selectors require a one-time first fire operation with voltage higher than the threshold voltage. Here, we introduce a novel SiOTe selector based on a stable silicon oxide matrix, with tunable first fire voltage and ultimately first fire-free characteristics. These selectors achieve low threshold voltages (V th = 1.1 V – 1.5 V) and low off-current (I off ~ 3 nA at 0.5 V for V th = 1.2 V). SiOTe selectors show promising thermal stability (300 °C, 30 min in air) and endurance of >108 cycles.
  • High speed (1ns) and low voltage (1.5V) demonstration of 8Kb SOT-MRAM array

    2022
    We demonstrated an 8Kb SOT-MRAM array which achieves the highest field-free switching speed (1ns) never reported. The low transistor switching voltage (V SW ) 1.5V at switching current density (J SW ) 68MA/cm2 is attributed to the unique tungsten-based cSOT channel material (SCM) which provides high spin-Hall angle (~0.6) and low resistivity (160μΩ-cm) with 400°C thermal budget. The 8Kb SOT-MRAM array also showed good read window and array yield thanks to the promising MTJ etching process. Excellent performances such as high retention ( >>10 years at RT) and high endurance 7e12 cycles are demonstrated as well.
  • Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array

    2022
    For the first time, we demonstrate Ferroelectric Tunneling Junctions (FTJs) with both (a) 10-year retention time projected from measured data and (b) robust endurance (> 108 cycles) with the on-off ratio >10× by inserting a 1.8nm Al 2 O 3 interfacial layer (IL) into the FTJs. Compared with Metal-Ferroelectric-Metal (MFM) FTJs, higher orthorhombic phase (~6×) was verified by physical analyses and first-principles calculations in our proposed Metal-Ferroelectric-IL-Metal (MFIM) FTJs, resulting in the remanent polarization (2P r ) which improves the retention and the on-off ratio significantly.
  • A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate FinFET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing

    2021
    A 16Kb one-time-programmable (OTP) antifuse memory is fabricated in a 5nm high-K, metal-gate FinFET CMOS for the first time. The bootstrap high voltage scheme (BHVS), read endpoint detection (REPD) and pseudo-differential sensing (PDS) are implemented to achieve intrinsic bit error rate (BER) below 1ppb for in-field programming in 5nm SoC and 10 years of data retention at 125°C.
  • CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference

    2021
    CHIMERA is the first non-volatile deep neural network (DNN) chip for edge AI training and inference using foundry on-chip resistive RAM (RRAM) macros and no off-chip memory. CHIMERA achieves 0.92 TOPS peak performance and 2.2 TOPS/W. We scale inference to 6x larger DNNs by connecting 6 CHIMERAs with just 4% execution time and 5% energy costs, enabled by communication-sparse DNN mappings that exploit RRAM non-volatility through quick chip wakeup/shutdown (33 μs). We demonstrate the first incremental edge AI training which overcomes RRAM write energy, speed, and endurance challenges. Our training achieves the same accuracy as traditional algorithms with up to 283x fewer RRAM weight update steps and 340x better energy-delay product. We thus demonstrate 10 years of 20 samples/minute incremental edge AI training on CHIMERA.
  • Characterization of Fatigue and Its Recovery Behavior in Ferroelectric HfZrO

    2021
    In this study, polarization fatigue of HfZrO ferroelectric is investigated with SILC (stress-induced-leakage-current) measurement under different E-field stresses. Under high-field, we observed strong correlation between polarization wake-up and SILC increase. This is attributed to oxygen vacancy redistribution and percolation path formation, especially at high frequency cycling. However, polarization fatigue at low field is found to occur without SILC increase. P-E loop measurements revealed that charge trapping is the main contributor under the low-bias. We demonstrated that the fatigue caused by low-field stress could be effectively recovered through an interspersed periodical, short-term cycles at high-field to manage charge trapping and oxygen vacancy redistribution, thus resulting in prolonged endurance to >1E12 cycles without SILC degradation at room temperature. We also validated that a negligible fatigue switching in HfZrO can be achieved at -40°C as low-temperature operation further reduces charge trapping.
  • Cold MRAM as a Density Booster for Embedded NVM in Advanced Technology

    2021
    Considering the improved performance of MTJs and access transistors for MRAM at low temperatures, we proposed a novel design for embedded Cold MRAM to boost the cell density to 5.3x of a conventional 6T-SRAM. Together with the CMOS operated at cryogenic conditions, they can provide a potential solution for the high demanding HPC applications.
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