Logic

High-performance and scaled transistors on carbon nanotube (CNT) channel are enabled by the quality of device component modules. This paper advances each module by single-CNT control experiments reporting: (1) remarkable n-type contact resistance of 5.1 kΩ/CNT(20.4Ω−μm for 250 CNT/μm) at 20 nm contact length, (2) tunable N-and Pdoping of CNT with dielectric doping, (3) improvement in top-gate dielectric interface to CNT by channel cleaning, (4) demonstration of channel comprised of dense CNT array with reduced bundle density, and (5) analysis of CNT bandgap tradeoffs with variability control strategy. The first component-complete pMOS FET is demonstrated on high-density CNTs with up to 680 μA/μm at -0.7V VDS.

Given the limited space and cooling capacity in dilution refrigerators, it is challenging to scale the number of qubits for a fault-tolerant quantum computer (QC). In this paper, we study a custom-scaled CMOS technology to overcome the constraints in the dilution refrigerators. With Cryo-Design/ Technology CoOptimization (Cryo-DTCO) in an advanced node, one can then reduce the control power from 26.8 mW/ qubit to 8.4 mW/ qubit (∼0.31×). Projections suggest this may be sufficient to enable error corrections via surface codes for fault-tolerant computing.

Two-dimensional transition metal dichalcogenides (2D TMDs) are expected to enable extremely scaled logic transistors for their ultrathin body and superior electrostatic control, i.e. gate length scaling. Aggressive scaling requires also contact length scaling. Here we demonstrate contact length scaling with low contact resistance of sub-100 Ω-μm (best data in TLM) through optimized surface preparation and semimetal/metal stack. Monolayer-MoS 2 channel transistors have the same driving current at contact length down to 30 nm. A calibrated TCAD model which captured device trends is used to extrapolate to ~250 Ω-μm at sub-15nm contact length per nanosheet of MoS 2 .

For the first time, a comprehensive TCAD model is developed to unambiguously extract key device parameters: contact resistance (R c ), channel mobility (μ CH ), Schottky barrier height (SBH), & D it from experimental data on back-gate (BG) transistors with MX 2 channel. The model is tested and validated against three different data sets with different contact metal, quality of channel, contact, and interfaces. Using model's output, we analyze the accuracy of R c and μ CH extracted by the TLM method and provide guidance on the limits of its applicability. Finally, the model is used to project contact requirements (SBH ~ 0eV, high doping density >2e13cm^-2 ) for performant, scaled transistors with 2D material channel in stacked nanosheet configuration.

Low-resistance p-type contacts to two-dimensional (2D) semiconductors remains a critical challenge towards the industrial application of 2D channel materials in advanced logic technology. To address this challenge, we computationally screen and identify designs for ultralow-resistance p-type contacts to 2D semiconductors such as WSe 2 by combining ab initio density-functional-theory (DFT) and quantum device simulations. Two new contact strategies, van der Waals metallic contact (such as 1H-NbS 2 ), and bulk semimetallic contact (such as Co 3 Sn 2 S 2 ), are identified as realistic pathways to achieving Schottky-barrier-free and low-contact-resistance p-type contacts for 2D semiconductor pFETs. Simulations of these new strategies suggest reduced metal-induced gap states, negligible Schottky barrier height and small contact resistance (down to ~20 Ω·μm). Preliminary experimental results in developing Co 3 Sn 2 S 2 as a new semimetal contact material are also demonstrated.

This work demonstrates the first successful integration of monolayer MoS 2 nanosheet FET in a gate-all-around configuration. At a gate length of 40nm, the transistor exhibits a remarkable I_ON∼410μA/μm at V_DS=1 V, achieved with a monolayer channel, ‘0.7 nm thin. The FET has a large I_ON/I_OFF>1E8, positive V_TH∼1.4 V with nearly zero DIBL. Higher drive current can be achieved through stacking of multiple channel layers. We propose here a fully integrated flow and we detail the feasibility of the most critical modules: stack/channel preparation, fin patterning, inner spacer, channel release, contact. The successful demonstration of MoS 2 NS with high performance and of the stacked NS modules further clarifies the value proposition in 2D materials for transistor scaling.

Low resistance contact technology for 2D semiconductors is a key bottleneck for the practical application of 2D channel materials at advanced logic nodes. This work presents a novel Sb-Pt modulated contact technology which can alleviate the Fermi-level pinning effect and mediate the band alignment at the metal-2D semiconductor interface, leading to exceptional ohmic contacts for both p-type and n-type WSe 2 FETs (p/n FET). WSe 2 FETs with different Sb/Pt contact compositions, in combination with new oxide-based encapsulation/doping technologies, exhibits record low pFET contact resistance of 0.75kΩ∙μm among all reported monolayer (1L) 2D pFETs. The nFET contact resistance of 1.8kΩ∙μm is also the lowest among 1L WSe 2 nFETs. Both 1L WSe 2 pFET and nFET demonstrated remarkable on-state p/n current ∼150μA/μm at |V_D|=1V, indicating the potential of WSe 2 for CMOS applications. A new version of the semi-automated dry transfer process for chemical vapor deposition (CVD) WSe 2 was also developed utilizing a novel Bi/PMMA/TRT support stack, offering low defect wrinkle-free WSe 2 transfer at wafer-scale.

Transistor scaling enabled by gate length scaling requires EOT scaling to less than 1 nm thickness [1]. This work successfully integrates Hf-based ALD higher-k dielectrics with CVD-grown monolayer (1L) MoS 2 to build top-gate nFET with EOT ~1 nm with nearly ideal subthreshold swing of 68 mV/dec. The gate stack described here achieves a high ε_eff ~13.53, a large E_BD ~12.4MV/cm, and excellent leakage current density. This is a remarkable performance among reported gate dielectrics on the transition metal dichalcogenides (TMDs) on which it is notoriously difficult to deposit a pinhole-free dielectric.

We present the first demonstration of p-MOSFET with a high ON current of 10⁻⁵A/um and good S.S. ∼80mV/dec. MOSFETs have the advantage of lower access resistance compared to Schottky barrier FETs. This requires spacer doping. Here, we introduce a self-limiting, fab-compatible process which consists of WO_x obtained from WSe₂ by O 2 plasma conversion. We analyze the process condition which enhance the doping effect. We quantify the doping level and the impact of the channel bandgap. We demonstrate a self-aligned version of the spacer doping for MOSFET fabrication.

Low-dimensional materials (LDMs) such as two-dimensional transition metal dichalcogenides (2D TMDs) and carbon nanotubes (CNTs) have the potential to be the channel material in extremely scaled CMOS transistors. Based on current hardware data, the design space for contacted-gate pitch (CGP) scaled transistors is explored for these materials. The ON current, sources of leakage which limit OFF current, and CGP scaling potential are analyzed by separately considering effects from shrinking the gate length, contact length, and extension length. Doping of LDM is the main challenge to reduce contact and extension resistance for scaled transistors. Experimental control of p-type doping of 2D is reported as an example of doping impact.