Logic

We present dielectric barrier booster for remote extension doping in low-dimensional materials (LDMs), e.g., ID Carbon Nanotubes (CNTs) and 2D MoS 2 . In contrast to prior work, the key idea is to "e;engineer"e; the thickness of a barrier layer (t BAR ) between LDM and dopant layer, in conjunction with the dopant layer itself, to optimize various remote extension doping trade-offs (e.g., transport, leakage, doping strength, parasitic load). Understanding such trade-offs requires extensive Design-Technology Co-Optimization (DTCO), not explored in prior literature. We explore a large space of ~50,000 design points through DTCO and derive various insights, including: (a) Barrier booster is key to enabling up to 1.5× energy-delay product (EDP) benefits for CNT FET ring oscillators vs. no-barrier case, (b) Barrier booster optimization depends on the target objective function: EDP optimization favors small t BAR (to increase extension charge density) while delay optimization favors large t BAR (to improve transport properties), (c) Doping guidelines derived from DTCO are LDM-specific: for example, we project 1.9× and 4.6× EDP benefits for extension-doped (with barrier booster) CNTs and MoS 2 , respectively, vs. undoped FETs. However, if EDP-optimal parameters for MoS 2 are used for CNTs (or vice-versa), the resulting EDP benefits are <1%.

For the first time, we demonstrate a transition metal dichalcogenide (TMD) Ferroelectric Field-Effect Transistor (FeFET) with ultra-high endurance (>10¹² measured) and retention time exceeding 10 years. The devices consist of an ultrathin Hf-Zr-based (HZO) ferroelectric deposited by ALD on a stack of AlO x /MoS 2 with process temperature <250°C. By using a 2.5nm HZO layer and a monolayer (1L) MoS 2 , a record-low operating voltage < 1V is reported thanks to excellent gate control. The device fabrication is compatible with Back-End-of-Line (BEoL) processes in advanced CMOS technologies. Array-level projections show that a sufficient memory window is maintained at a supply voltage (V DD ) of IV. This device has promise for high-density memory embedded in scaled CMOS technology nodes.

For the first time we report degenerate and self-aligned doping in the sub-20nm spacer region on a high-density CNT channel to achieve high-performance CNT p-MOSFET with I D = 12 mA/μm at V DS = -0.75 V, CGP = 160 nm, and L G = 50 nm. The extension doping lowers the effective energy barrier height near the contact from 228 meV to 50 meV. The parasitic resistance remains 250 Ω•μm for contact lengths ranging from 100 nm to 20 nm. Calculated intrinsic gate delay (τ=RC=CV/I, including gate and spacer capacitances) based on resistance and spacer capacitance values of experimental structures, indicate that the doped-spacer MOSFET enables intrinsic gate delay ~2× lower vs. SBFET and ~2.6× lower vs. undoped-spacer MOSFET. These benefits are even more significant for shorter channel lengths. Strategies for overcoming channel quality and gate interface non-idealities are discussed.

Low n-type contact resistance (R C ) of 9.7 kΩ/CNT to carbon nanotubes (CNT) with short contact length (L C ) of 20 nm is achieved by utilizing solid-state n- doping near the metal contact. AIN doping with barrier layer demonstrated in this work enables transparent electron conduction for both Pd and Ti metal contacts. We systematically explore doping strength control with barrier thickness, R C trends scaling down to 20 nm L C , CNT bandgap dependence of doping, and device stability for insight into electrical impact of key process parameters. Symmetric R C n- and p-FET reveals a clear path to meet IRDS target for 2034 device roadmap.

This work demonstrates the first stacked nanosheet devices with monolayer MoS 2 channel after successful simultaneous release of 2 nanosheets. Two-stacked monolayer MoS 2 nanosheets with 50-nm width can be released free up to 150 nm, proving excellent mechanical properties of the channel material. Conformal gate stack deposition on the 2-stacked MoS 2 sheets is confirmed. To increase contact area, we introduce here ‘C-type’ wrap-around contact that contacts not only the edge but also the top and bottom side on the monolayer MoS 2 channels. For the first time, studies of gate stack and its impact on subthreshold swing, threshold voltage and hysteresis are presented on single nanosheet gate all around (GAA) devices. Unlike most reports in literature of depletion-mode monolayer MoS 2 devices, through appropriate process control and interface engineering we report here positive threshold voltage for NMOS devices.

Two-dimensional (2D) transition metal dichalcogenide (TMD) materials are regarded as promising channel candidates for extreme contacted gate pitch (CGP) scaling. However, basic demonstration of the modules required to build logic devices is limited. For the first time, we demonstrate comparable n-type and p-type high-performance on 2D transistors. Translation to 300 mm wafer processing is tested by die-by-die transfer of the 2D material. The 300 mm fabrication preserves a relatively high mobility of 30 cm 2 /V•s. We demonstrate scaling of nMOS contact length (L C ) to 12 nm and top gate length (L G ) to 10 nm. Devices maintain high current density at short L C as well as in top-gate only operation.

High-performance and scaled transistors on carbon nanotube (CNT) channel are enabled by the quality of device component modules. This paper advances each module by single-CNT control experiments reporting: (1) remarkable n-type contact resistance of 5.1 kΩ/CNT(20.4Ω−μm for 250 CNT/μm) at 20 nm contact length, (2) tunable N-and Pdoping of CNT with dielectric doping, (3) improvement in top-gate dielectric interface to CNT by channel cleaning, (4) demonstration of channel comprised of dense CNT array with reduced bundle density, and (5) analysis of CNT bandgap tradeoffs with variability control strategy. The first component-complete pMOS FET is demonstrated on high-density CNTs with up to 680 μA/μm at -0.7V VDS.

Given the limited space and cooling capacity in dilution refrigerators, it is challenging to scale the number of qubits for a fault-tolerant quantum computer (QC). In this paper, we study a custom-scaled CMOS technology to overcome the constraints in the dilution refrigerators. With Cryo-Design/ Technology CoOptimization (Cryo-DTCO) in an advanced node, one can then reduce the control power from 26.8 mW/ qubit to 8.4 mW/ qubit (∼0.31×). Projections suggest this may be sufficient to enable error corrections via surface codes for fault-tolerant computing.

Two-dimensional transition metal dichalcogenides (2D TMDs) are expected to enable extremely scaled logic transistors for their ultrathin body and superior electrostatic control, i.e. gate length scaling. Aggressive scaling requires also contact length scaling. Here we demonstrate contact length scaling with low contact resistance of sub-100 Ω-μm (best data in TLM) through optimized surface preparation and semimetal/metal stack. Monolayer-MoS 2 channel transistors have the same driving current at contact length down to 30 nm. A calibrated TCAD model which captured device trends is used to extrapolate to ~250 Ω-μm at sub-15nm contact length per nanosheet of MoS 2 .

For the first time, a comprehensive TCAD model is developed to unambiguously extract key device parameters: contact resistance (R c ), channel mobility (μ CH ), Schottky barrier height (SBH), & D it from experimental data on back-gate (BG) transistors with MX 2 channel. The model is tested and validated against three different data sets with different contact metal, quality of channel, contact, and interfaces. Using model's output, we analyze the accuracy of R c and μ CH extracted by the TLM method and provide guidance on the limits of its applicability. Finally, the model is used to project contact requirements (SBH ~ 0eV, high doping density >2e13cm^-2 ) for performant, scaled transistors with 2D material channel in stacked nanosheet configuration.