Logic

Logic

TSMC has been at the forefront of advanced CMOS logic technologies for which dense transistors are one of the two essential building blocks, the other being dense interconnect stacks. The intrinsic computing capability of a given logic technology is directly related to the number of interconnected transistors and their switching speed under representative loads originating from both the transistor or gates being driven and the related interconnect resistive and capacitive circuit loads.

TSMC research and development is continuously exploring novel and scalable transistor concepts to ensure sustainable, cost-effective, leading-edge logic technology performance and energy efficiency. We invite you to explore some of TSMC research areas in transistor structure, high-mobility channel, and low-dimensional materials and devices.

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  • Wafer-scale single-crystal hexagonal boron nitride monolayers on Cu (111)

    2020
    Ultrathin two-dimensional (2D) semiconducting layered materials offer great potential for extending Moore’s law of the number of transistors in an integrated circuit1. One key challenge with 2D semiconductors is to avoid the formation of charge scattering and trap sites from adjacent dielectrics. An insulating van der Waals layer of hexagonal boron nitride (hBN) provides an excellent interface dielectric, efficiently reducing charge scattering2,3. Recent studies have shown the growth of single-crystal hBN films on molten gold surfaces4 or bulk copper foils5. However, the use of molten gold is not favoured by industry, owing to its high cost, cross-contamination and potential issues of process control and scalability. Copper foils might be suitable for roll-to-roll processes, but are unlikely to be compatible with advanced microelectronic fabrication on wafers. Thus, a reliable way of growing single-crystal hBN films directly on wafers would contribute to the broad adoption of 2D layered materials in industry. Previous attempts to grow hBN monolayers on Cu (111) metals have failed to achieve mono-orientation, resulting in unwanted grain boundaries when the layers merge into films6,7. Growing single-crystal hBN on such high-symmetry surface planes as Cu (111)5,8 is widely believed to be impossible, even in theory. Nonetheless, here we report the successful epitaxial growth of single-crystal hBN monolayers on a Cu (111) thin film across a two-inch c-plane sapphire wafer. This surprising result is corroborated by our first-principles calculations, suggesting that the epitaxial growth is enhanced by lateral docking of hBN to Cu (111) steps, ensuring the mono-orientation of hBN monolayers. The obtained single-crystal hBN, incorporated as an interface layer between molybdenum disulfide and hafnium dioxide in a bottom-gate configuration, enhanced the electrical performance of transistors. This reliable approach to producing wafer-scale single-crystal hBN paves the way to future 2D electronics.
  • Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs

    2020
  • Enabling Multiple-Vt Device Scaling for CMOS Technology beyond 7nm Node

    2020
  • 7nm Mobile SoC and 5G Platform Technology and Design Co-Development for PPA and Manufacturability

    2019
    We report on Qualcomm® Snapdragon™ SDM855 mobile SoC and world's first commercial 5G platform using industry-leading 7nm FINFET technologies. SDM855 exhibits CPU performance gain over the previous generation thanks to a new design architecture enabled by dual poly pitch process integration. Low voltage operation and tight spread in power consumption has been achieved through process and design co-development, delivering a high performance and low power solution for both mobile and AI applications. Extending the 7nm technology with 2 nd -year process enhancement demonstrates up to 50mV CPU Vmin reduction without any change to design rules, which paves the road for an integrated 5G mobile platform with connectivity.
  • Sn Incorporation in Ultra-Thin InAs Nanowires for Next-Generation Transistors characterized by Atom Probe Tomography

    2019
    Growth of ultrathin semiconducting nanowires (NWs) and incorporation of dopants suitable for future CMOS scaling targets (diameter <20 nm) is a challenge. Limits on dopant incorporation in thin NWs have led to concerns about the suitability of these structures. In this work, the atomic structure of the thinnest InAs NWs ever reported, down to 7 nm diameter, is characterized using transmission electron microscopy (TEM) and atom probe tomography (APT). It is demonstrated that there is no fundamental limit of Sn incorporation into ultrathin InAs NWs. Additionally, the Sn distribution of the Au catalyst particle controlling the growth is characterized.
  • Monolithic Heterogeneous Integration of BEOL Power Gating Transistors of Carbon Nanotube Networks with FEOL Si Ring Oscillator Circuits

    2019
    High performance carbon nanotube (CNT) network transistors with on-resistance (R on ) of <; 250 Ω are successfully integrated as back-end-of-the-line (BEOL) power gating devices onto Si CMOS wafers manufactured using 28-nm process technology. When the power supply is connected through the BEOL CNT network header array, the front-end-of-the-line (FEOL) Si ring oscillators (ROs) achieve a similar quiescent current (I DDQ ) and have the comparable active power (P ACTIVE ) consumption under the same operation frequency as compared to the operation without the power gating CNT transistors. The fabrication of CNT devices in the BEOL is verified to cause no performance degradation in the underlying FEOL Si CMOS devices. This study has successfully demonstrated heterogeneous integration of advanced Si logic circuits with low-cost and high-mobility CNT transistors in the BEOL fabricated at low, BEOL-compatible temperatures (250 °C).
  • Key Technology Enablers of Innovations in the AI and 5G Era

    2019
    The proliferation of AI and the deployment of 5G networks accelerate the transformation of our society into a highly connected world. Semiconductors are the indispensable elements in realizing all the product innovations. The progress and challenges of the state of art CMOS technology and advanced packaging, considered as critical pillars to continue the improvement of system functions, will be reviewed.
  • 5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021um2 SRAM cells for Mobile SoC and High Performance Computing Applications

    2019
    A leading edge 5nm CMOS platform technology has been defined and optimized for mobile and HPC applications. This industry-leading 5nm technology features, for the first time, full-fledged EUV, and high mobility channel (HMC) finFETs with densest 0.021μm 2 HD SRAM. This true 5nm CMOS platform technology is a full node scaling from our successful 7nm node [4] in offering ~1.84x logic density, 15% speed gain or 30% power reduction. The 5nm platform technology successfully passed qualification [3] with consistently high yielding 256Mb HD/HC SRAM, and large logic test chip consisting of CPU/GPU/SoC blocks. Currently in risk production, this true 5nm platform technology is on schedule for high volume production in 1H 2020.
  • A High-Performance InAs/GaSb Core-Shell Nanowire Line-Tunneling TFET: An Atomistic Mode-Space NEGF Study

    2019
    Using a tight-binding mode-space NEGF technique, we explore the essential physics, design and performance potential of the III-V core-shell (CS) nanowire (NW) heterojunction tunneling field-effect transistor (TFET). The CS TFET “line-tunneling” current increases significantly with the core diameter d C and outperforms the best III-V axial “point-tunneling” NW heterojunction TFET I ON by up to 6× for d C = 6.6 nm. Reaching such a high level of current at low supply voltage, however, requires and involves specific and sometime unanticipated optimizations and physics that are thoroughly investigated here. In spite of the commonly accepted view, we also show and explain the weak gate-length dependency observed for the line-tunneling current in a III-V TFET. We further investigate the effect of electron-phonon scattering and discrete dopant impurity band tails on optimized CS NW TFETs. Including those non-idealities, the CS-TFET inverter performance significantly outperforms that of the axial TFETs. The low-power (LP) V DD = 0.35V CS-inverter delay is comparable to that of the high-performance (HP) Si CMOS using V DD = 0.55, which shows promise for an LP TFET technology with HP speed.
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