Heterogeneous Integration of a Compact Universal Photonic Engine for Silicon Photonics Applications in HPCOne of the prominent challenges for widespread adoption of Si photonics (SiPh) technology is the availability of an integration platform that can simultaneously meet a wide range of power, performance, and cost criteria in different applications. As a result, there is a diversity of Si photonics integrated solutions proposed or demonstrated, but none is considered as a common solution. In this paper, we will first survey industry proposed photonic engine (PE) structures in monolithic, 2D, 2.5D, and 3D on their strengths and weaknesses. We will then propose a compact and universal PE structure- COUPE (COmpact Universal Photonic Engine) that could consolidate different requirements onto the same integration platform. COUPE has the EIC-PIC integration with the electrical interface designed to minimize the EIC-PIC coupling loss. Compared with industry proposed PE technology, COUPE can provide low insertion loss for both grating coupler (GC) and edge coupler (EC). For either GC or EC, the COUPE is a solid structure without cavities or mechanically weak parts, thus enabling low insertion loss without contamination or mechanical concerns. COUPE also has the flexibility to be integrated easily with host ASIC to form a co-package structure. The COUPE integration scheme can meet the most demanding system requirements and pave the way for silicon photonics based wafer level system integration (WLSI) for high performance computing (HPC) applications.
Electromigration-Induced Bit-Error-Rate Degradation of Interconnect Signal Paths Characterized from a 16nm Test ChipAn array-based test-vehicle for tracking bit-error-rate (BER) degradation of signal interconnects subject to DC electromigration (EM) stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. BER measurement results from four individual interconnect paths are presented and analyzed.
Ultra High Power Cooling Solution for 3D-ICsA direct silicon water cooling solution using fusion bonded silicon lid is proposed. It is successfully demonstrated as an effective cooling solution with total power >2600 W on a single SoC, equivalent to power density of 4.8 W/mm2. Low temperature logic chip to silicon lid fusion bonding, with trench/grid cooling structure cutting into silicon lid enables minimal thermal resistance between active device and cooling water and best cooling efficiency. Direct water cooling on logic chip silicon backside has also been demonstrated with power density better than 7 W/mm2.
Advance Patterning Approach for Cu/Low-k interconnectsThe RC delay, electro migration (EM) and TDDB performance become more challenges to meet device requirement as continuous geometry shrink on BEOL dual damascene interconnects. To overcome these challenges from interconnect patterning point of view, we proposed Cu subtractive RIE as a potential solution for next generation Cu/Low-k interconnects.
Ultra-thin ALD-MnN Barrier for Low Resistance Advanced Interconnect TechnologyAs dimension shrinks the volume percent occupied by conventional barrier and liner increases and line resistance (Rs) and via resistance (Rc) increases dramatically. An ultrathin ALD MnN barrier is being evaluated as a single layer barrier for resistance reduction in small structures. >20% and >80% Rs and Rc reduction was demonstrated, while 4× better mean time to failure (MTTF) on the time dependent dielectric breakdown (TDDB) was achieved comparing to conventional barrier/liner. ALD MnN is a potential barrier candidate for future interconnects technology.
Low-via-resistance and low-cost PVD-TiZrN barrier for Cu/low-K interconnectsIn this work, a low-resistance and low-cost PVD-TiZrN barrier is evaluated for BEOL interconnect. Comparing to conventional PVD barrier, comparable Cu barrier and Cu wetting properties are obtained. Moreover, up to 55% of via resistance reduction is achieved, with comparable voltage breakdown performance comparing to conventional one.
A flexible top metal structure to improve ultra low-k reliabilityHigh stresses generated from chip-package interactions (CPI), especially when large die is flip mounted on organic substrate using Pb-free C4 bumps, can easily cause low-k delamination. A novel scheme by applying an elastic material can effectively reduce the transmitted stresses and, thus, resolve the interfacial delamination issue. Along with an optimized chip-package integration solution, a reliable interconnect structure with good electrical performance, has been successfully demonstrated.
A novel LWR reduction approach to enhance reliability performance in ultra-thin barrier/porous low-k (K<2.4) interconnectThis study evaluated plasma treatment processes on 193i and EUV photoresist to improve the line width roughness (LWR) performance in porous low-k/ultra-thin barrier Cu interconnect. We successfully demonstrated 20% LWR reduction for 193i PR and 11% for EUV PR. Furthermore, the influence of LWR on reliability was evaluated on 45nm line-width test vehicle. A boost of 10 times Time Dependent Dielectric Breakdown (TDDB) and 2 times Eelectrical Migration (EM) was demonstrated.
Uncured ELK as a chemical mechanical planarization stop layer in Cu/XLK interconnectA novel approach of copper CMP stop layer using uncured extreme low-K was demonstrated to improve the within-wafer Rs uniformity on Cu/extra low-k (XLK) interconnect. This CMP stop layer could be converted into a low dielectric constant film by removing porogen with post CMP treatment, hence its impact on overall’s film capacitance is minimized.
Low damage etch approach for next generation Cu interconnectThis research focus on low radical plasma etch (LRPE) process and its impact on highly porous dielectric material (extreme-low-k, ELK, k=2.4). We demonstrate a dual damascene (DD) process flow without k degration by low radical and pore sealing plasma etch. Comparing to tranditional DD etching process, 12% resistance-capacitance (RC) improvement, 15% via resistance reduction and a factor of 3 inter-metal-dielectric (IMD) time dependent dielectic breakdown (TDDB) improvement can be achieved by the proposed approach.
On-chip interconnect today is based on copper/low-k wiring – in today’s chips, there can be more than 100 km of copper wires.
TSMC’s leading edge technologies use a novel copper gap-fill solution to enable the fabrication of smaller conductor lines. Newly-developed materials and processes allow significant reduction in line and via resistance to improve chip performance. A comprehensive suite of innovations on integration scheme, low-k material, and low-k process with selective deposition further enhance both performance (through capacitance reduction) and reliability. Beyond copper interconnect, explorations of single metallic elements, binary and ternary alloys, and 2D materials for future interconnect materials are underway both within TSMC and with our academic partners.