Events

21st century applications are going to be data-centric. Data analytics, machine learning, and AI applications are going to dominate, from data center to mobile and IoT, from collecting and processing, to curating the data to derive information. Many systems will need to learn and adapt on the fly. The emergence of abundant-data computing made the system throughput and system throughput/Watt the key performance metrics. These metrics can be improved by more and more specialization from CPU to GPU, to TPU and accelerators that are able to execute a narrow set of tasks in a massively parallel fashion. In other words flexibility can be traded off to maximize system throughput and energy efficiency. Computation throughput has been advancing faster than the memory bandwidth, resulting in a bandwidth deficit that limits system performance. With this in mind, this presentation will look at how the performance of those specialized architectures can be improved at the system level by advances of the underlying device and process technologies. An analysis of the technology trend for GPU and accelerators leads to a key observation: in the coming decades, we must go beyond a single chip from a wafer and focus on integrating chips into systems. 3DIC will unleash architecture innovations in computing.

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The foundry business model, pioneered by TSMC more than three decades ago, brought a sea change to technology innovation and how integrated circuits (ICs) and systems are designed and manufactured. Access to semiconductor technology is no longer limited to large corporations that invest billions of dollars to build a fabrication plant. The foundry model has democratized IC innovation, making it available to all visionaries and innovators. Today, an open innovation platform that connects innovators with semiconductor-technology providers is a vital link in the global supply chain. Our industry has already begun to look beyond just engineering individual chips manufactured on wafers, and have moved to integrate individual chips into systems. System performance and energy efficiency will continue to advance at historical rates, driven by innovations from many aspects, including materials, device and integration technology, circuit design, architecture, and systems. User applications drives design choices, and design choices are enabled by technology advancements. Advances in an open innovation ecosystem will further lower the entry barriers and unleash the future of innovation.

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Semiconductor technology migration is challenged by SoC Scaling, along with power, thermal and memory walls. Chiplets integration is a feasible resolution to address those issues. However, chiplet technology need innovation and leverage to achieve the goal. In this paper, we present foundry 3DFabric™ 2.5/3/3+ solutions to integrate chiplets for near- and long-term need. Close collaboration among the supply chain are strongly encouraged. We also propose a 3DIC (3D Interconnect Density) migration roadmap for industry and academia to align overall research and development activities.

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Three dimensional integration is one of the major technology directions for integrated circuits. From 2.5D integration on the package level to 3D integration by chip stacking and wafer stacking using processes in the far-back-end and monolithic 3D integration using back-end-of-the-line and front-end-of-the-line processes, there is a range of connection density that spans over 7 to 8 orders of magnitude. In other words, there is plenty of room for advancement for 3D ICs. I will give an overview of the semiconductor technologies that may need to be developed to realize monolithic 3D integration with the highest possible connection density between device layers. I will speculate on how they will be integrated into future electronic systems.

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While 5G and Artificial Intelligence (AI) technologies individually reshape industries and experiences, collectively 5G and AI are, perhaps, the most globally disruptive and transforming force that we’ve seen in decades. IC innovation focusing on energy efficient scaling will continue to power these changes that are revolutionizing our daily lives. Our future requires stronger partnerships across entire semiconductor ecosystem.

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In the past few decades, the semiconductor industry has been extremely successful in integrating discrete components into billion-transistor chips following a well-defined path – shrinking the transistor. It is no longer the case that the logic transistor is the only driver for technology advances. In the coming decades, we must go beyond a single chip on a wafer and focus on integrating chips into systems. I will describe the major technology trends and outline some of the solutions for advancing energy efficiency of future electronic systems.

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Future electronic systems will continue to rely on, and increasingly benefit from, the advances in semiconductor technology as they have had for more than five decades. Since its inception, the semiconductor industry has used a physical dimension (minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. Density is what drives the benefits of new device technologies for computation – the primary application driver for semiconductors. Going forward, we will use a three-prong metric that consists of logic density (DL), memory bit density (DM), and interconnect density between logic and memory (DC) as a means to capture how advances in semiconductor device technologies enable system level benefits. Because DL and DM will increase at a slower rate than the historical trends, technologies that address the connectivity will become primary drivers for technology advancement. This trend is already visible in HPC products that progressively leverage more capable packaging technologies including 3D chip stacking. Indeed, vertical interconnect density associated with advanced packaging featured about three orders of magnitude improvement in the last decade alone. Scaling vertical interconnect pitch to sub-100 nm would enable another four orders of magnitude improvement. As such, there is plenty of room for system-level advances based on 3D ICs. The distinction between on-die connectivity (vias and on-chip interconnect wires) and off-chip connectivity (e.g. TSVs and micro-bumps) will become increasingly blurred. Wafer-level monolithic integration technologies and packaging technologies will smoothly blend into one another. New design tools that optimally perform system partitioning will become indispensable.

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Packaging technology used to play mainly a protection role in the supply chain for IC, which follows the path of Moore’s Law with system-on-chip. When chip scaling becomes more challenging and, at the same time, we want to integrate more functions such as memory, sensors and passives, etc. for new applications such as AI and 5G, etc, innovative heterogeneous integration technologies are proposed for system-on-package to provide critical PPA values of the micro-systems. We are making far-reaching changes, which initiate an exciting new semiconductor era and create a new industry landscape.

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Internet of things and artificial intelligence demand further performance improvements in integrated circuit systems. One ongoing effort is to continue the transistor scaling with either new device architectures or adopting new materials with superior gate controllability. Another attractive approach is to construct three-dimensional integrated circuits (3D ICs) with monolithic integration; for example, adding sensor functionalities, or constructing upper-layer logic circuits or memory devices on CMOS Si wafers. The research on materials and processes compatible with the backend-of-line (BOEL) fabrication temperature (< 400 oC), is urgently needed. In this presentation, I like to discuss on few potential components useful for achieving monolithic 3D ICs including 2D layered materials such as transition metal dichalcogenide based semiconductors, hexagonal boron nitride (hBN) insulators, and 1D semiconducting carbon nanotubes. The proof-of-concept monolithic integration of carbon nanotube transistors on our 28 nm CMOS technology wafers has also been demonstrated.

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