Collaboration Programs

SystemX emphasizes application-driven, system-oriented research. Its areas of interest include hardware and software at all levels of the system stack from materials and devices to systems and applications in electronics, networks, energy, mobility, bio-interfaces, sensors, and other real-world domains.

Vision for Non-volatile Memory Technology Research Initiative aims at dealing with challenges of increasing needs for embedded memory with high density and low cost with power minimization by forming an interdisciplinary team of faculty, staff and students to look into technical feasibility at the device level, circuit/system level as well as develop a fundamental understanding for a variety of new non-volatile memory phenomena, materials and processes.

New concepts for more energy-efficient logic switches (transistor replacements) and more energy-efficient on-chip communication (interconnect replacements) are needed to extend and go beyond the era of Moore’s Law. In addition to breakthroughs in solid-state science and technology, innovations in circuit design and system architecture will be necessary to avert a power crisis for computing. Focus areas of the center include the Looming Power Crisis for Computing, Advent of the Internet of Things, and Proliferation of Big Data Applications.

The center is focused on developing compact modeling solutions for advanced semiconductor devices. The BSIM (Berkeley Short-channel IGFET Model) Group develops physics-based, accurate, scalable, robust, and predictive MOSFET SPICE models for circuit simulation and CMOS technology development.

The Georgia Tech 3D Systems Packaging Research Center focuses on Smart, wearable, IOT, automotive, bio-electronics, and high-performance systems research. Focus areas are Electrical, Mechanical, and Thermal Design; Low-cost Glass Interposer and Package; Interconnections and Assembly; Functional Components - Passives and their Integration with Actives; 3D Glass Photonics; and MEMS and Sensors – High-power and High-temperature Electronics.

MTL is predicated on the notion that nanoscale science and technology can help solve some of the world’s greatest problems in areas of energy, communications, water, health, information, and transportation. The focus is on fundamental research and engineering in materials, structures, devices, circuits and systems. MTL’s activities encompass integrated circuits, systems, electronic and photonic devices, MEMS, bio-MEMS, molecular devices, nanotechnology, sensors, and actuators.

The MIT AI Hardware Program is an academia-industry initiative dedicated to disruptive innovations in artificial intelligence hardware. The mission is innovating technologies that deliver enhanced energy efficiency systems for computing in the cloud and at the edge. The approach is based on use-inspired research, where the corporate members create new projects with MIT researchers or expand existing activities. Projects span the full abstraction stack: materials, devices, circuits, algorithms and software.

Purdue University has launched the Center for Secure Microelectronics Ecosystem (CSME) with support from industry partners and a U.S. Department of Defense (DOD)-funded workforce development program. CSME is a first-of-its-kind global partnership of academia, industry and government to advance research and workforce development in designing secure microelectronics. Its aim is to help ensure a secure supply of semiconductor chips and related products and tools, from the foundry to the packaged system, based on a zero-trust model.

Arizona State University is home to various centers and institutes that blend the passions of exceptional faculty and scholars across disciplines. Our centers and institutes address large, complex problems and challenges facing society in hopes of finding solutions and making the world a better place. From pursuing cutting-edge research in earth and space exploration, developing quick solutions to fight new infectious diseases, to studying implications of new discoveries on public policy and democracy, our centers and institutes are working toward positive change locally, nationally, internationally, and beyond.

The Center for Aggressive Scaling by Advanced Process for Electronics and Photonics (ASAP) is working to strengthen U.S. leadership in critical technologies — including high-performance computing, advanced manufacturing, 5G and beyond — by creating new materials and process paradigms for efficient electrical interconnects, photonic integration, and in-memory computing solutions targeting digital, analog, and RF platforms.

Starting from the application space, the design environment, and the integration scheme, appropriate new materials and components are being developed. These include energy sources, memory, sensors, passives, electromechanical and medical devices. UCLA CHIPS has pioneered the dielet revolution and develops new methodologies and infrastructure for integrating dielets (sometimes also called chiplets) at pitches comparable to on-chip wiring levels, enabling both latencies, bandwidth and energy per bit comparable to monolithic integration, but at the board level. CHIPS center has developed integration platforms for both rigid electronics based on silicon, flexible platforms based on bio-compatible materials, and monolithic 3D integration using wafer-to-wafer bonding for memory scaling and cognitive applications.  

The Center for Domain-Specific Computing (CDSC) looks beyond parallelization and focuses on domain-specific customization as the next disruptive technology to bring orders-of-magnitude power-performance efficiency improvement to important application domains. The recent focus is on design and implementation of accelerator-rich architectures, from single chips to data centers. It also includes highly automated compilation tools and runtime management software systems for customizable heterogeneous platforms, including multi-core CPUs, many-core GPUs, and FPGAs, as well as a general, reusable methodology for customizable computing applicable across different domains.

The major research interest of the Center include: 2D material, 2D devices, band structure analysis and simulation, emerging Si- & SiGe-based transistor, nanosheet transistor, backend interconnect, graphene, self-assembled monolayer molecule, high-K dielectric deposition, stacking of 3D electronics, ferroelectric material & memory, atomic layer technologies, negative capacitance FET, quantum computing using Si qubit, and synchrotron radiation photoemission studies on high-k/semiconductor interfaces.

The major research interests include: monolithic stacked devices and circuits, negative-capacitance FETs, two-dimensional material field-effect transistors, 2D contact engineering, low-resistance interconnect technology, low contact resistance technology, and FinFETs technology for high speed and high frequency applications.

Research interests focus on computing in memory, computing in sensor, neuromorphic computing, and advanced embedded computing to improve the combination of speed and power consumption by orders of magnitude, EUV negative resist with potential of high light absorption rate, small resist blur and thin resist film, EUV interference imaging platform, e-beam imaging platform and micro detector array for process improvement, etc. The Center also conducts more than 10 JDPs annually.

The research focuses are quantum computing and RF circuit research & development. That includes fundamental qubit devices to the integration of multiple qubits, qubit test, noise analysis, cryo-CMOS device and modeling, design and integration of 24-GHz sensor RF receiver system, 24-GHz sub-circuits of LNA, PA, VCO, Mixer, PLL and its sensing application etc. The Center also conducts more than 10 JDPs annually.

imec aims to push Moore’s law to the extreme by scaling logic devices to the 2nm technology node and far beyond. Selected topics of device-related research are:

• Extending Si technology beyond Nanosheet FETs, such as Complementary FET (CFET)
• Novel channel materials, such as 2D-dichalchonenides and Carbon Nanotube FET (CNT FET)
• Assessment of Design and system level PPA benefits

A view of the Logic Technology Roadmap can be found here

Within the memory IIAP, imec develops novel memory concepts aimed for increased memory density, while at the same time controlling power dissipation. These new memory elements are based on a wide variety of, sometimes recently discovered and thus new, physical properties and require new materials and device integration development. Current topics that are part of the program are:

• High speed embedded on-chip cache memory such as SOT-MRAM
• Scaled high speed dynamic random access memory (DRAM) devices
• New Storage-class memories for massive data access in short time, such as Ferroelectric RAM (FERAM)
• Improved NAND Flash memory devices for high performance and mobile devices: high density, low-cost, low-power & non-volatile

Within the IIAP on advanced lithography imec works together with industry leaders to tackle the lithography challenges:

• Explore materials and processes for next generation pattering
• Assess manufacturability of high-NA EUV lithography and readiness for high volume manufacturing
• Evaluate/compare lithographic imaging and patterning solutions for advanced logic and memory applications

Moreover, ASML and imec (sites are located at close vicinity) have been partners for more than 30 years. In 2013, imec and ASML launched the Advanced Patterning Center, combining imec’s and ASML’s complementary expertise, engineering teams and patterning infrastructure to tackle upcoming scaling challenges towards single digit nanometer dimensions.

Due to ever increasing economic and technical issues the classical scaling of CMOS technology may slow down. To keep reducing the cost per function, one possibility is to move to a 3-dimensional stacking of ICs (3D-IC). Using 3D chip stacking, it is possible to extend the number of functions per 3D chip well beyond the near-term capabilities of traditional scaling. Additionally, smart system partitioning into multiple stacked tiers provide a power-performance benefit.

In the 3D IC IIAP, imec explores cost-effective realization of 3D interconnect technology with through-silicon-via (TSV) and novel backside contact schemes. imec also explores 3D design to propose methodologies for critical design issues, enabling effective use of 3D interconnection on system level:

• Electrical, thermal and thermo-mechanical characterization and optimization
• Fine-pitch Die-to-wafer and wafer-to-wafer technologies
• Chip-package interaction
• 3D-aware EDA and test

As logic and memory nodes scale, the performance of advanced interconnects is negatively impacted by increasing interconnect resistance and capacitance. Furthermore, high current densities in ultra-scaled metal wires and vias leads to reliability concerns. The IIAP on advanced interconnects aims to explore together with industry leaders the options to increase bandwidth density and improve power performance for reliable high speed distribution of signals within scaled logic and memory devices. Focus is on:

• Beyond-Cu metals
• Integration schemes beyond dual damascene
• Low-k and air gap interlayer dielectrics

Some applications are too complex to be solved with classical computing. Quantum computing could come to the rescue. In a quantum computer, information is manipulated with qubits that are in a superposition of “0” and “1”, rather than in only one of those states like classical bits. Add to this entanglement, which means that qubits talk with each other and act concertedly, and the number of states in a quantum registry increases like a power law with the number of qubits. Operations can thus be performed in immense parallelization capability, giving the potential for quantum computing the ability to solve those big problems. imec’s platform for CMOS processing is a unique basis for quantum computer. In imec’s Quantum Computing IIAP, silicon technology forms the base for development of a quantum computer technology and initially a Si compatible wafer-scale qubit demonstration is pursued.

To keep up with Moore’s law, the semiconductor industry continues to push the envelope in developing new device architectures containing novel materials. This in turn pushes the need for new solid-state analytical capabilities, whether for materials characterization or inline metrology. Aside from basic R&D, these capabilities are established at critical points of the semiconductor device manufacturing line, to measure, for example, the thickness and composition of a thin film, dopant profiles of transistor’s source/drain regions, the nature of defects on a wafer’s surface, etc. imec supports the IIAP by the development and implementation of tomorrows materials characterization techniques. Some examples include:

• New Materials Modelling including fundamental understanding via ab-initio or ML algorithms for massive data screening
• The deployment of novel Scanning Probe Microscopy capabilities to support 2D materials R&D
• The implementation of the novel SIMS approaches for array profiling
• The transfer of micro-4-point-probe for local sheet resistance characterization to the fab environment
• The development of high resolution Rutherford Backscattering Spectroscopy (RBS) and RBS array profiling capabilities
• The examination of enhancement effects noted in Raman when applied to confined volume analysis

In its optical I/O program, imec develops the technology to enable these future optical interconnects. In the first place, they’re meant for high-performance and data center systems, and for rack-to-rack, within-rack, and within-board connections. One of the key challenges is making cost-efficient packages. To do so, imec is looking at wafer-scale solutions leveraging the methods developed in its 3D system integration program.

Automotive semiconductor technologies are crucial to making mobility more sustainable, safe, and affordable. Silicon performance is rapidly replacing horsepower as the foremost differentiator between car models. The compute performance needed to drive next-generation ADAS/AD and in-vehicle infotainment (IVI) is immense. Soon, every car will need a supercomputer on board, which cannot solely run on chips that rely on monolithic IC design. Chiplet architectures, combining chips designed to perform specific functions efficiently, will allow car OEMs to aim for cost-effective systems tailored to the demands of various applications. And quickly adapt those systems across car models and model generations by swapping chiplets, not unlike LEGO blocks.

Digital solutions can be used to address environmental and climate issues. Therefore, semiconductor technology is a vital ingredient for a more sustainable future. But what about our industry’s own environmental impact? imec has estimated that IC manufacturing could account for 3% of total greenhouse gas emissions by 2040. That’s partly due to the growth of the industry. But it’s also linked to the fact that the process behind every new technology node becomes more complex and more energy-intensive. And let’s not forget that the semiconductor industry’s ecological repercussions go beyond its contribution to climate change. They also include high water consumption, depletion of abiotic resources and generation of e-waste. To address the sustainability of the semiconductor industry, imec’s SSTS program takes a three-pronged approach: 1) Assess – making a virtual fab; 2) Improve with real solutions for the actual fab floor; 3) Disrupt with a new generation of sustainable technologies for the future fab.