On-chip Interconnect

On-chip interconnect today is based on copper/low-k wiring – in today’s chips, there can be more than 100 km of copper wires.

TSMC’s leading edge technologies use a novel copper gap-fill solution to enable the fabrication of smaller conductor lines. Newly-developed materials and processes allow significant reduction in line and via resistance to improve chip performance. A comprehensive suite of innovations on integration scheme, low-k material, and low-k process with selective deposition further enhance both performance (through capacitance reduction) and reliability. Beyond copper interconnect, explorations of single metallic elements, binary and ternary alloys, and 2D materials for future interconnect materials are underway both within TSMC and with our academic partners.

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  • Advance Patterning Approach for Cu/Low-k interconnects

    The RC delay, electro migration (EM) and TDDB performance become more challenges to meet device requirement as continuous geometry shrink on BEOL dual damascene interconnects. To overcome these challenges from interconnect patterning point of view, we proposed Cu subtractive RIE as a potential solution for next generation Cu/Low-k interconnects.
  • Ultra-thin ALD-MnN Barrier for Low Resistance Advanced Interconnect Technology

    As dimension shrinks the volume percent occupied by conventional barrier and liner increases and line resistance (Rs) and via resistance (Rc) increases dramatically. An ultrathin ALD MnN barrier is being evaluated as a single layer barrier for resistance reduction in small structures. >20% and >80% Rs and Rc reduction was demonstrated, while 4× better mean time to failure (MTTF) on the time dependent dielectric breakdown (TDDB) was achieved comparing to conventional barrier/liner. ALD MnN is a potential barrier candidate for future interconnects technology.
  • Low-via-resistance and low-cost PVD-TiZrN barrier for Cu/low-K interconnects

    In this work, a low-resistance and low-cost PVD-TiZrN barrier is evaluated for BEOL interconnect. Comparing to conventional PVD barrier, comparable Cu barrier and Cu wetting properties are obtained. Moreover, up to 55% of via resistance reduction is achieved, with comparable voltage breakdown performance comparing to conventional one.
  • A flexible top metal structure to improve ultra low-k reliability

    High stresses generated from chip-package interactions (CPI), especially when large die is flip mounted on organic substrate using Pb-free C4 bumps, can easily cause low-k delamination. A novel scheme by applying an elastic material can effectively reduce the transmitted stresses and, thus, resolve the interfacial delamination issue. Along with an optimized chip-package integration solution, a reliable interconnect structure with good electrical performance, has been successfully demonstrated.
  • A novel LWR reduction approach to enhance reliability performance in ultra-thin barrier/porous low-k (K<2.4) interconnect

    This study evaluated plasma treatment processes on 193i and EUV photoresist to improve the line width roughness (LWR) performance in porous low-k/ultra-thin barrier Cu interconnect. We successfully demonstrated 20% LWR reduction for 193i PR and 11% for EUV PR. Furthermore, the influence of LWR on reliability was evaluated on 45nm line-width test vehicle. A boost of 10 times Time Dependent Dielectric Breakdown (TDDB) and 2 times Eelectrical Migration (EM) was demonstrated.
  • Uncured ELK as a chemical mechanical planarization stop layer in Cu/XLK interconnect

    A novel approach of copper CMP stop layer using uncured extreme low-K was demonstrated to improve the within-wafer Rs uniformity on Cu/extra low-k (XLK) interconnect. This CMP stop layer could be converted into a low dielectric constant film by removing porogen with post CMP treatment, hence its impact on overall’s film capacitance is minimized.
  • Low damage etch approach for next generation Cu interconnect

    This research focus on low radical plasma etch (LRPE) process and its impact on highly porous dielectric material (extreme-low-k, ELK, k=2.4). We demonstrate a dual damascene (DD) process flow without k degration by low radical and pore sealing plasma etch. Comparing to tranditional DD etching process, 12% resistance-capacitance (RC) improvement, 15% via resistance reduction and a factor of 3 inter-metal-dielectric (IMD) time dependent dielectic breakdown (TDDB) improvement can be achieved by the proposed approach.
  • A new enhancement layer to improve copper interconnect performance

    This study reports the effect of different barrier on Cu interconnect performance. A thin “enhancement” layer of Ru or Co film is deposited between a PVD Ta(N) liner barrier and a Cu seed layer to improve copper to barrier adhesion and copper gap fill. With the enhancement layer of either Ru or Co, no void is found in dual damascene structure with very thin seed. The electrical performance is improved with more than two times of EM lifetime is observed. The seedless electroplating on the enhancement layers capability will maximize the gap fill window.
  • Challenges of Low Effective-K approaches for future Cu interconnect

    Challenges of various low effective-K approaches, including homogeneous low-K and air-gap, for next generation Cu/low-K interconnect will be presented. For homogeneous low-K approach, top issues and possible solutions for K damage, package, and CMP peeling & planarization due to introduction of fragile lower k (KLt2.4) insulator will be focused. For air-gap, various types of air-gaps will be reviewed from the points of cost, layout/designer, and new processes involved.
  • Low capacitance approaches for 22nm generation Cu interconnect

    Various integration approaches, including homogeneous porous Low-k and air gaps, for low-capacitance solution were investigated for 22 nm Cu interconnect technology and beyond. For homogeneous Low-k approach, K=2.0 Low-k material is successfully integrated with Cu. Up to 15% line to line capacitance reduction compared with LK-1 (K= 2.5) was demonstrated by a damage-less etching and CMP process. For air gap approach, a cost-effective and Selective air gaps formation process was developed. Air gaps are selectively formed only at narrow spacing between conduction lines without additional processes.
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