Logic

A leading edge 2nm CMOS platform technology (N2) has been developed and engineered for energy-efficient compute in AI, mobile and HPC applications. This industry-leading N2 logic technology features energy-efficient gate-all-around nanosheet (NS) transistors, middle-of-line and backend-of-line interconnects with densest SRAM macro of ~38Mb/mm2. N2 delivers a full node benefit from previous 3nm node [2] in offering 15% speed gain or 30% power reduction with >1.15x chip density increase. N2 platform technology, equipped a new Cu scalable-RDL (sRDL), flat passivation and TSVs, co-optimizes holistically with 3DFabricTM technology enabling system integration/ scaling for AI/mobile/HPC product designs. N2 successfully met wafer-level reliability requirements and passed 1000hrs HTOL qual with high yielding 256Mb HC/HD SRAM (~>90%), and logic test chip (>3B gates) consisting of CPU/GPU/ SoC blocks. Currently in risk production, N2 platform technology is scheduled for mass production in 2H’25. N2P, 5% speed enhanced version of N2 with full GDS compatibility, targets to complete qualification in 2025 and mass production in 2026.

This study presents the first functional advanced CFET inverter with an industry-leading 48nm gate pitch, exhibiting well-balanced voltage transfer characteristics up to 1.2 V. In this paper, we elaborate on the advancements in our nanosheet-based monolithic complementary field-effect transistor (mCFET) process architecture, which builds upon our previous work. Key developments include a vertical dipole patterning process for independent n/p threshold voltage tuning, a vertical metallized drain local interconnect for n/p epitaxy connection at the common drain, and backside middle-of-line contacts and interconnects that improve performance and increase design flexibility. A comprehensive evaluation of the electrical performance of the mCFET devices with different configurations validates the effectiveness of our integrated process architecture. The successful demonstration of fully operational mCFET inverters marks an important milestone in the pioneering of CFET technology, paving the way for future logic technology scaling and the advancement of power, performance, area, and cost (PPAC).

Notable progress has been reported for n-type contacts to two-dimensional (2D) materials, either through doping or through careful choice of contact metals. Here, we report on p-type contact engineering via substitutional doping and alloying. We tune the dopant concentration from lightly to heavily doped WSe2. We demonstrate that bilayer (2L) transition metal dichalcogenide (TMD) alloy can reach degenerate doping density for WSe2. The degenerate doping plays a critical role in lowering contact resistance (Rc) to metal. Extracted Rc is ~98 Ω·μm for a sheet resistance (Rsh) of 4.5 kΩ/sq, independent of the gate voltage (Vg). Pd/alloy contacts show superior thermal stability when compared to typical semimetal contacts (Bi and Sb).

In this work, a systematic non-conductive stress (NCS) is applied to understand NCS acceleration lifetime model for circuit applications at off-state high drain bias. The study revealed that elevated NCS could led to a rise in off-state channel current (IDOFF) caused by reverse hot carrier injection, affecting potential standby leakage. The examination of NCS influence on device degradation and the exploration of lowering NCS effects by reducing ISOFF was conducted. A study on a wide voltage range NCS validated the ISOFF and VDG accelerated IDOFF degradation lifetime model. The defined reliability boundary based on application-specific mission profiles provides guidance on the "Design for Reliability" (DFR) workflow for optimizing circuit design to mitigate off-state reliability risks before multi-project-wafer verification.

Amorphous oxide semiconductor field-effect transistors (AOSFETs) exemplify the trade-off between mobility, stability, and threshold voltage (VTH). In this work, a new 5-axes AOSFET evaluation framework for back-end-of-line (BEOL) integration is proposed, including (i) ID extracted at a fixed over-drive beyond VTH at 1 pA/um for performance, (ii) IOFF, (iii) VTH, (iv) subthreshold slope (SS) at 1V VDS for off-state behaviors, and (v) VTH shift under positive bias stress for stability. To break the trade-off between mobility and VTH, an oxide capping layer and post-capping anneal are used on back-gated W-doped In2O3 (IWO) FETs. The oxide capping and anneal demonstrate stoichiometry-independent positive VTH shift on 1% and 2% IWO channel FETs by 0.85V and 0.4V, respectively, while mobility increases from 18.5 to 26 cm2V-1s-1 for 1% IWO. The contact resistance is also lowered from 2185 Ω-µm to 967 Ω-µm, enabling ION increase by 1.42×. With the oxide capping and anneal, the stability under positive bias stress improves by 300 mV to -67 mV VTH shift. An enhancement-mode 1% IWO FET is shown at 55 nm LCH with positive VTH = 0.53V, low IOFF = 160 pA/µm, ID = 192 µA/µm at 1E13 cm-2 charge density, and ID = 50 µA/µm extracted at a fixed over-drive voltage beyond 1 pA/um at 1V VDS.

This paper provides a history of transistor innovations extending up to the present time and a look into the future of CMOS logic technology requirements for long-term sustainable growth on system-level integration, performance, and energy-efficiency, focusing on beyond-silicon MOSFETs and heat management research challenges. Applied research aimed to identify a transistor family that can replace and support sustainable energy-efficiency, performance, and density beyond the foreseeable silicon-based CMOS scaling is of up most importance. Equally important is stepping up efforts to establish scalable energy-efficient CMOS compatible memory element solutions that can address the logic-embedded SRAM and DRAM memory space. Sustainable increases in device counts per chip will require commensurate innovations on heat spreading and management to support the multilayer stacking dimension.

Carbon nanotubes (CNTs) show great promise as channel material for future highly scaled transistors due to their atomic-thin body, high carrier mobility, and high injection velocity for both electrons and holes. In this work, we achieve ID greater than 300μA/μm at +/-1V VDS (iso-performance) for both N-type and P-type MOSFETs with 100nm gate length (LG) on densely aligned CNT array by self-aligned extension doping with a barrier booster [1]. Our process only modifies the extension dopant and contact metal to alter the device polarity while maintaining iso-performance. We also present the first experimental validation of tunable doping strength, mobility loss minimization, and leakage reduction capabilities of the barrier booster method, studied for top-gate CNT N-type MOSFET in this paper. Using this method, we achieve the best performance to date for N-type MOSFET on densely aligned CNT array, with ID>200μA/μm and Imax/Imin exceeding 104 simultaneously at 1V VDS and 500nm LG. With future improvements to the dielectric interface quality and device scaling, the benefits of CNT CMOS technology may be fully realized.

Efficient digital circuits require CMOS transistors with well-matched threshold voltage (VTH). In this work, we demonstrate for the first time CMOS co-integration, and well-matched VTH showcased through inverters based two-dimensional (2D) materials with supply voltage (VDD) of 1 V. We compare the fabrication of these circuits using the same channel material with using dedicated N and P channel materials (hetero-channel). Both instances use monolayer 2D transition metal dichalcogenide. The hetero-channel inverters allow superior performance at a relevant VDD = 1 V: voltage gain exceeding 10 V/V, noise margin over 80%, low average static-power consumption ~ 7 pW, and a switching voltage (VM) ~ 0.5 V. While still far from Si performance, reaching these numbers simultaneously requires multiple step developments working well together for monolayer 2D materials in the co-integrated flow. Sensitivity of various electrical metrics to process steps is also discussed in the paper.

This report presents the first electrical demonstration of a stacked nanosheet (NS) FET with a monolayer MoS2 channel, utilizing a typical nanosheet release process prior to high-k metal gate deposition. We demonstrate the fabrication of flat, two-stacked nanosheets with a monolayer MoS2 channel and a conformal HfOX/TiN gate stack. The stacked nanosheets, with a width of 100 nm, exhibit good release behavior, allowing for an integration scheme that supports gate lengths of up to 250 nm. IMAX/IMIN ratios of ~1E5 and a subthreshold swing of ~220 mV/dec are reported. Additionally, for the first time, the integration of stacked two NS WSe2 and two NS MoS2 in the same structural FET is demonstrated using the NS release and high-k metal gate conformal deposition process. The two channel materials represent typical PMOS and NMOS 2D materials, respectively.

We report the first direct extraction of CNT MOS interface metrics normalized to CNT length or CNT surface area using statistical impedance modeling and analysis of lateral capacitors measured between 100 and 300 K. Direct Dit extraction from impedance is a crucial step towards high performance CNT MOSFETs and is enabled by (1) a statistical approach towards modeling of CNT impedance, (2) a capacitor architecture meeting the requirements for Dit extraction, and (3) the extension of impedance acquisition to below 1 fF. A rigorous model treatment of surface potential fluctuations s in depletion due to fixed charge and CNT diameter variations allows to reproduce C-V features, to elucidate the physics, and to reconcile SS obtained from I-V curves with impedance data by extending the standard SS equation. CNT midgap Dit normalized to CNT surface area of  71012 cm¬-2 eV-1 and increasing towards the band edge to above 51013 cm-2 eV-1, s standard deviation s  2.5 kT, and a midgap capture length of 0.01 nm are extracted. Preliminary process optimizations demonstrate a positive impact on the Dit vs E curve.