Memory

Data is the most valuable resource in today’s digital economy. Currently over 2.5 quintillion (1018) bytes of data are generated daily and the pace is accelerating. More data than ever needs to be processed. Memory plays a key role in the flow of data. The gap between logic and memory is a bottle neck to system performance. To optimize the trade-off between cost and performance, a hierarchical memory system has been adopted. At the top of the hierarchy are static random access memories (SRAM) and dynamic random access memory (DRAM), both inherently volatile. SRAM is integrated right on the logic chips as cache memory to provide fastest access. DRAM is physically smaller than SRAM and consequently supports higher capacity. DRAM is generally an off-chip memory solution and ~10x slower than SRAM due to the need for constant refresh. Non-volatile memories (NVM) such as Flash are next in the hierarchy providing much higher memory capacity and density while also preserving information in the absence of power.

Recent new technologies are emerging rapidly to bring processing tasks near to or inside the memory to improve computing efficiency and enable new functionalities. Emerging NVMs use new types of materials and mechanisms to store data. They are promising for blending the memory hierarchy to boost the overall performance. Furthermore, their unique characteristics offer great potential to enable new applications (e.g. neuromorphic computing) and novel architectures (e.g. 3D integration).

TSMC’s non-volatile memory solutions include Flash, Spin-transfer torque magnetic random access memory (STT-MRAM), and resistive random access memory (RRAM). TSMC is also actively exploring phase change random access memory (PCRAM), and spin-orbit torque MRAM (SOT-MRAM) elements, as well as selector devices which are essential to support higher density cross-point array architectures.

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  • Demonstration of Ferroelectric FET Memory with Oxide Semiconductor Channel to Achieve Smallest Cell Area 0.009 μm2 and High Endurance for Non-Volatile High-Bandwidth Memory Applications

    2024
    Here we experimentally demonstrate a smallest cell area of 0.009 μm2 in ferroelectric (FE) FET memory device with oxide semiconductor (OS) channel (OS-FeFET) and achieve high read current to 40 μA/μm, program speed below 30 ns, and >1000 s data retention at 85 ℃ fabricated by BEOL-compatible processes on 300-mm wafer. We show that the asymmetric dipole switching issue inherent to lack of hole carriers in n-type OS can be effectively mitigated by phase engineering in Hf(1-x)ZrxO2 (HZO) film to attain highly reproducible switching behaviors with reduced operation voltage. The endurance of OS-FeFET can be significantly improved by interface layer (IL) and HZO film engineering to minimizing the generation and migration of oxygen vacancy, leading to outstanding endurance towards 1012 cycles. This work paves way to realize BEOL-compatible memory with high density and low-power consumption.
  • First Demonstration of an N-P Oxide Semiconductor Complementary Gain Cell Memory

    2024
    This work presents the first experimental demonstration of a Complementary Gain Cell (CGC) memory utilizing an n-type oxide semiconductor transistor (OSFET) as the write transistor and a p-type OSFET as the read transistor. Complementary (n-p) polarities effectively mitigate capacitive coupling of gain cells utilizing voltage sensing. Atomic Layer Deposition (ALD) Indium Tungsten Oxide (IWO) for nFET and Physical Vapor Deposition (PVD) Tin Oxide (SnO) for pFET are utilized. The ALD IWO nFET has a positive Vth of ∼1.15 V and subthreshold slope (SS) of ∼80 mV/dec. The fabricated SnO pFET has an Ion/Ioff ratio >5e4. The CGC achieves a measured retention time of 10,000 seconds under a −0.5 V write word line (WWL) standby voltage and can mitigate the WL capacitive coupling issue. The use of both n-type and p-type OS transistors for the 2T gain cell enables the potential for multilayer monolithic 3D integrated memory, paving the way for future “chip city” developments.
  • MRAM Design-Technology-System Co-Optimization for Artificial Intelligence Edge Devices

    2024
    STT-MRAM shows great promise for use in artificial intelligence (AI) edge devices due to its compact bitcell area and high endurance. However, it faces read challenges because of its low TMR and RP. Conventional sense amplifiers have limitations in optimizing read energy and robustness while providing flexibility to exploit neural-net error tolerance. This article explores the design challenges of conventional sense amplifiers and examines how device parameters (TMR and RP) impact read performances. A novel capacitive-coupling sense amplifier is introduced to offer a new design space for balancing read energy and robustness. Combining the exploitation of neural-net error tolerance with sense amplifier and device co-design, a Design-Technology-System Co-Optimization (DTSCO) approach demonstrates a read energy reduction of 27.1% to 45.3% with minimal inference accuracy degradation in edge AI applications
  • High RA Dual-MTJ SOT-MRAM devices for High Speed (10ns) Compute-in-Memory Applications

    2023
    The rapid development of artificial intelligence in recent decades has been continuously driving new software and hardware advancements. High-dimensional matrix-vector multiplication (MVM) is a crucial component in signal processing and machine learning computations. To achieve MVM, the 2D crossbar array of memristors has been widely discussed and studied. In this work, a novel SOT-MRAM device structure with 10ns write speed and >100x scalable resistance and read current are demonstrated to address the persistent problems of the traditional 2D crossbar array, leveraging its read-write path separation nature.
  • High-Endurance MoS2 FeFET with Operating Voltage  Less Than 1V for eNVM in Scaled CMOS Technologies

    2023
    For the first time, we demonstrate a transition metal dichalcogenide (TMD) Ferroelectric Field-Effect Transistor (FeFET) with ultra-high endurance (>1012 measured) and retention time exceeding 10 years. The devices consist of an ultrathin Hf-Zr-based (HZO) ferroelectric deposited by ALD on a stack of AlO x /MoS 2 with process temperature <250°C. By using a 2.5nm HZO layer and a monolayer (1L) MoS 2 , a record-low operating voltage < 1V is reported thanks to excellent gate control. The device fabrication is compatible with Back-End-of-Line (BEoL) processes in advanced CMOS technologies. Array-level projections show that a sufficient memory window is maintained at a supply voltage (V DD ) of IV. This device has promise for high-density memory embedded in scaled CMOS technology nodes.
  • Low voltage (<1.8 V) and high endurance (>1M) 1-Selector/1-STT-MRAM with ultra-low (1 ppb) read disturb for high density embedded memory arrays

    2023
    Integrating STT-MRAM with low voltage 2-terminal selector is a promising approach to boost embedded memory integration density. This work presents a new low voltage 1-Selector/1-STT-MRAM (1S1R) device based on SiNGeCTe (SNGCT) chalcogenide threshold selector. Remarkable 1S1R device performance is demonstrated under voltage pulse operation. For the first time, 1e9 read disturb- free cycles are experimentally demonstrated in STT-MRAM-based 1S1R. Moreover, the new device proves low voltage, high speed, low write error rate (<9 ppm at 1.7 V/ 50 ns), along with excellent write endurance (>1M cycles).
  • Low voltage (<1.8 V) and high endurance (>1M) 1-Selector/1-STT-MRAM with ultra-low (1 ppb) read disturb for high density embedded memory arrays

    2023
    Integrating STT-MRAM with low voltage 2-terminal selector is a promising approach to boost embedded memory integration density. This work presents a new low voltage 1-Selector/1-STT-MRAM (1S1R) device based on SiNGeCTe (SNGCT) chalcogenide threshold selector. Remarkable 1S1R device performance is demonstrated under voltage pulse operation. For the first time, 1e9 read disturb- free cycles are experimentally demonstrated in STT-MRAM-based 1S1R. Moreover, the new device proves low voltage, high speed, low write error rate (<9 ppm at 1.7 V/ 50 ns), along with excellent write endurance (>1M cycles).
  • Direct Quantitative Extraction of Internal Variables from Measured PUND Characteristics Providing New Key Insights into Physics and Performance of Silicon and Oxide Channel Ferroelectric FETs

    2022
    We propose a new approach where internal distributed variables of ferroelectric FETs (FEFET) are directly extracted from measured positive-up negative-down (PUND) FEFET and ferroelectric capacitor (FECAP) P-V data. Quantitative energy band diagrams (EBDs) reveal the detailed device physics by providing internal device quantities including potential, polarization, carrier density, and defect density in energy and real space at each external bias point. The insights into internal device quantities shed light onto the intricate symbiosis between polarization switching and charge emission/capture, stress induced memory window closure due to permanently trapped charge and/or interface/channel defect generation; and phenomena including read delay after write, polarization switching, and polarization walkout/snapback. The new key findings provide a path into possible solutions of performance and lifetime limitations of both Si and oxide channel FEFETs.
  • Engineering defects in pristine amorphous chalcogenides for forming-free low voltage selectors

    2022
    Amorphous chalcogenide-based threshold selectors are among the most promising two-terminal technologies for high density non-volatile memories. However, the necessity of a high voltage forming operation makes their implementation in low voltage logic chips a key challenge. This work reports a new approach towards forming-free chalcogenide selectors, where extra defects are introduced to assist the forming process and reduce the forming voltage. The added defects are shown to increase the conductivity of the pristine chalcogenide and can be annihilated after the first switching pulse operation. Forming-free low voltage selectors based on SiNGeCTe (SNGCT) chalcogenide are demonstrated along with excellent endurance characteristics over 1010 cycles.
  • Endurance > 1011 Cycling of 3D GAA Nanosheet Ferroelectric FET with Stacked HfZrO2 to Homogenize Corner Field Toward Mitigate Dead Zone for High-Density eNVM

    2022
    After 1011 high endurance cycles with memory window (MW) =0.9 V is achieved for the 3D gate-all-around (GAA) nanosheet (NS) ferroelectric field-effect transistor (FeFET) based on double-HZO; the aim is to homogenize the corner field and mitigate dead zones. The interlayer Al 2 O 3 or TiN in the double-HZO exhibits MW enhancement or low access voltage, respectively. The proposed MFMFS GAA-FeFET demonstrates a low V P/E = ±3.5 V (±2.3 MV/cm), large MW = 1.3 V, >1011 robust endurance cycles, and stable storage with data retention of >2×104 s; therefore, physical dimension scaling of the embedded nonvolatile memory (eNVM) is feasible for future generations.
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