A 40nm 2Mb ReRAM Macro with 85% Reduction in FORMING Time and 99% Reduction in Page-Write Time Using Auto-FORMING and Auto-Write SchemesThis work proposes (1) an auto-forming (AF) scheme to shorten the macro forming time (TFM-M) and testing costs; (2) an auto-RESET (ARST) scheme to shorten page-RESET time (TW-PAGE-RST) for expanding the applications of hidden-RESET operation in standby mode, and (3) an auto-SET (ASET) scheme to shorten page-write time (TW-PAGE) combined with hidden-RESET scheme. A fabricated 40nm 2Mb ReRAM macro achieved 85+% reduction in T FM - M , and 99+% reduction in TW-PAGE for a page. For the first time, AF, ARST, and ASET schemes are demonstrated in silicon for ReRAM.
The combination of AI (Artificial Intelligence) and IoT (the Internet of Things) referred as AIoT is a powerful duo that may fuel the growth of the semiconductor industry for years to come. High-capacity on-chip memories with low power consumption are required for energy-efficient machine learning. It can support both 1T1R (1 transistor + 1RRAM) and 1S1R (1 selector + 1RRAM) array architectures. Compared to the conventional 1T1R architecture, the 1S1R architecture can achieve higher density and enable 3D integration. TSMC, in collaboration with a technology partner, has developed RRAM memory technology on a 40nm CMOS logic backbone to support application-specific needs. TSMC continues to explore novel RRAM material stacks and their density-driven integration, along with variability-aware circuit design and programing constructs to realize high-density embedded RRAM-based solution options for AIoT applications.