Low Dimensional Material & Device

Transistor research team at TSMC is also exploring devices built on materials having intrinsically 2D or 1D carrier transport (low-dimensional transport). Transition metal dichalcogenides, graphene nanoribbons, and carbon nanotubes, among others, are being investigated theoretically and experimentally. TSMC research work is both internally conducted and/or in collaboration with our academic partners through joint development projects, or by active technical participation in leading research consortia or research institutes worldwide. Here we invite you to explore some of TSMC’s recent published work in these fields of active exploratory research.

The benefits of using 2D and 1D materials include high mobility at atomic thickness, excellent gate control, and potential applications for low-power and high-performance devices. Thus, transistor scaling may be extended. In a recent publication, we have successfully demonstrated the growth of wafer-scale h-Boron Nitride monolayer, which is able to efficiently protect the channel 2D semiconductors from process damages and the charge impurity scattering from adjacent dielectrics. 1D semiconducting carbon nanotubes, with processes compatible with the backend-of-line (BOEL) fabrication temperature (< 400 oC), are a potential component for achieving monolithic 3D ICs. The proof-of-concept monolithic integration of carbon nanotube transistors on our 28 nm CMOS technology wafers has also been demonstrated.

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  • High Performance Transistor of Aligned Carbon Nanotubes in a Nanosheet Structure

    2024
    This work demonstrates the first nanosheet FET built on an array of dense aligned carbon nanotubes. In this device structure, the gate surrounds an aligned array of CNTs with ≈300CNT/μm . At a channel length of 70 nm the drive current exceeds 1mA/μm at -0.5 V VDS with sub- VT slope of 135 mV/dec, and an IMIN of 76nA/μm.RC of 20.5Ω−μm is extracted by transmission line method. This is record-high performance for transistors with CNT channel. However, reducing DIT and channel variability are necessary to enable energy-efficient CMOS applications.
  • On the extreme scaling of transistors with monolayer MoS2 channel

    2024
    2D transition metal dichalcogenides (TMDs) show promise for transistor scaling, but their on-scale performance had not been proven yet. This work demonstrates contact length (Lc) scaling while holding a low contact resistance (R C ) down to 11 nm. Channel length (LCH) scaling shows I ON can increase down to at least 12 nm with low Rc. The very scaled (CH =19 nm and C=12 nm) Mos2 transistor with Sb-based metal contact has current density of ~1130 μA/μm at VDS = 1 V, and a low RC of ~ 190 Ω.μm. These scaled transistors, processed within a back-end-of-line (BEOL) thermal budget, do not exhibit subthreshold swing (S.S.) degradation or observable drain-induced barrier lowering (DIBL) down to LCH=12nm.
  • P-type SnO Semiconductor Transistor and Application (Invited)

    2024
    In this work, high-quality p-type SnO material is developed by PVD deposition. Sub-l00 nm short channel p-SnO devices are first demonstrated with current density 1 0~20 µA/µm, Ion/Ioff over 104 , SS ~0.4 V/dec and hole mobility~2 cm2 /V s. The monolithic 3D integration with oxide transistors in BEOL benefits FPGA, reducing its chip area and leakage while causing trivial overhead to its performance.
  • Barrier Booster for Remote Extension Doping and its DTCO in 1D & 2D FETs

    2023
    We present dielectric barrier booster for remote extension doping in low-dimensional materials (LDMs), e.g., ID Carbon Nanotubes (CNTs) and 2D MoS 2 . In contrast to prior work, the key idea is to "e;engineer"e; the thickness of a barrier layer (t BAR ) between LDM and dopant layer, in conjunction with the dopant layer itself, to optimize various remote extension doping trade-offs (e.g., transport, leakage, doping strength, parasitic load). Understanding such trade-offs requires extensive Design-Technology Co-Optimization (DTCO), not explored in prior literature. We explore a large space of ~50,000 design points through DTCO and derive various insights, including: (a) Barrier booster is key to enabling up to 1.5× energy-delay product (EDP) benefits for CNT FET ring oscillators vs. no-barrier case, (b) Barrier booster optimization depends on the target objective function: EDP optimization favors small t BAR (to increase extension charge density) while delay optimization favors large t BAR (to improve transport properties), (c) Doping guidelines derived from DTCO are LDM-specific: for example, we project 1.9× and 4.6× EDP benefits for extension-doped (with barrier booster) CNTs and MoS 2 , respectively, vs. undoped FETs. However, if EDP-optimal parameters for MoS 2 are used for CNTs (or vice-versa), the resulting EDP benefits are <1%.
  • High-Endurance MoS2 FeFET with Operating Voltage  Less Than 1V for eNVM in Scaled CMOS Technologies

    2023
    For the first time, we demonstrate a transition metal dichalcogenide (TMD) Ferroelectric Field-Effect Transistor (FeFET) with ultra-high endurance (>1012 measured) and retention time exceeding 10 years. The devices consist of an ultrathin Hf-Zr-based (HZO) ferroelectric deposited by ALD on a stack of AlO x /MoS 2 with process temperature <250°C. By using a 2.5nm HZO layer and a monolayer (1L) MoS 2 , a record-low operating voltage < 1V is reported thanks to excellent gate control. The device fabrication is compatible with Back-End-of-Line (BEoL) processes in advanced CMOS technologies. Array-level projections show that a sufficient memory window is maintained at a supply voltage (V DD ) of IV. This device has promise for high-density memory embedded in scaled CMOS technology nodes.
  • High-performance and low parasitic capacitance CNT MOSFET: 1.2 mA/µm at VDS of 0.75 V by self-aligned doping in sub-20 nm spacer

    2023
    For the first time we report degenerate and self-aligned doping in the sub-20nm spacer region on a high-density CNT channel to achieve high-performance CNT p-MOSFET with I D = 12 mA/μm at V DS = -0.75 V, CGP = 160 nm, and L G = 50 nm. The extension doping lowers the effective energy barrier height near the contact from 228 meV to 50 meV. The parasitic resistance remains 250 Ω•μm for contact lengths ranging from 100 nm to 20 nm. Calculated intrinsic gate delay (τ=RC=CV/I, including gate and spacer capacitances) based on resistance and spacer capacitance values of experimental structures, indicate that the doped-spacer MOSFET enables intrinsic gate delay ~2× lower vs. SBFET and ~2.6× lower vs. undoped-spacer MOSFET. These benefits are even more significant for shorter channel lengths. Strategies for overcoming channel quality and gate interface non-idealities are discussed.
  • Low N-Type Contact Resistance to Carbon Nanotubes in Highly Scaled Contacts through Dielectric Doping

    2023
    Low n-type contact resistance (R C ) of 9.7 kΩ/CNT to carbon nanotubes (CNT) with short contact length (L C ) of 20 nm is achieved by utilizing solid-state n- doping near the metal contact. AIN doping with barrier layer demonstrated in this work enables transparent electron conduction for both Pd and Ti metal contacts. We systematically explore doping strength control with barrier thickness, R C trends scaling down to 20 nm L C , CNT bandgap dependence of doping, and device stability for insight into electrical impact of key process parameters. Symmetric R C n- and p-FET reveals a clear path to meet IRDS target for 2034 device roadmap.
  • Monolayer-MoS2 Stacked Nanosheet Channel with C-type Metal Contact

    2023
    This work demonstrates the first stacked nanosheet devices with monolayer MoS 2 channel after successful simultaneous release of 2 nanosheets. Two-stacked monolayer MoS 2 nanosheets with 50-nm width can be released free up to 150 nm, proving excellent mechanical properties of the channel material. Conformal gate stack deposition on the 2-stacked MoS 2 sheets is confirmed. To increase contact area, we introduce here ‘C-type’ wrap-around contact that contacts not only the edge but also the top and bottom side on the monolayer MoS 2 channels. For the first time, studies of gate stack and its impact on subthreshold swing, threshold voltage and hysteresis are presented on single nanosheet gate all around (GAA) devices. Unlike most reports in literature of depletion-mode monolayer MoS 2 devices, through appropriate process control and interface engineering we report here positive threshold voltage for NMOS devices.
  • Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel

    2023
    Two-dimensional (2D) transition metal dichalcogenide (TMD) materials are regarded as promising channel candidates for extreme contacted gate pitch (CGP) scaling. However, basic demonstration of the modules required to build logic devices is limited. For the first time, we demonstrate comparable n-type and p-type high-performance on 2D transistors. Translation to 300 mm wafer processing is tested by die-by-die transfer of the 2D material. The 300 mm fabrication preserves a relatively high mobility of 30 cm 2 /V•s. We demonstrate scaling of nMOS contact length (L C ) to 12 nm and top gate length (L G ) to 10 nm. Devices maintain high current density at short L C as well as in top-gate only operation.
  • Building high performance transistors on carbon nanotube channel

    2023
    High-performance and scaled transistors on carbon nanotube (CNT) channel are enabled by the quality of device component modules. This paper advances each module by single-CNT control experiments reporting: (1) remarkable n-type contact resistance of 5.1 kΩ/CNT(20.4Ω−μm for 250 CNT/μm) at 20 nm contact length, (2) tunable N-and Pdoping of CNT with dielectric doping, (3) improvement in top-gate dielectric interface to CNT by channel cleaning, (4) demonstration of channel comprised of dense CNT array with reduced bundle density, and (5) analysis of CNT bandgap tradeoffs with variability control strategy. The first component-complete pMOS FET is demonstrated on high-density CNTs with up to 680 μA/μm at -0.7V VDS.
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