Impact of SMT-induced edge dislocation positions to NFET performance
This work highlights the impact of SMT-induced edge-dislocation positions in nFET device design. Based on experimental results and atomic transport simulation, dislocations with reduced proximity and depth would increase the amount of SFs and TDs which induce high parasitic resistance and high I boff leakage current together. Trade-off among strained mobility, parasitic resistance and I boff should be made for advanced device design.
Ab initio study of dipole-induced threshold voltage shift in HfO2/Al2O3/(100)Si
The ab initio work quantitatively explains the physical mechanism of threshold voltage shifts in n-type and p-type metal-oxide-semiconductor field-effect transistors with HfO 2 /Al 2 O 3 gate stack. In the study, the θ phase alumina has been chosen for better lattice matching of the (100) HfO 2 and (100) Si substrate. Using dipole correction method, the dominant dipole moment responsible for the threshold voltage shift has been identified at the interface of HfO 2 /Al 2 O 3 . Our HfO 2 /Al 2 O 3 atomic model shows the dipole moment decreases almost linearly as the alumina thickness decreases from four monolayers (13 Å) to one monolayer (3 Å). On account of the effects of capacitance and the dipole moment, our ab initio calculation quantitatively explains the trend and sensitivity of experimental threshold voltage shifts on n- and p-MOSFET's.
CMOS-Compatible GaN-on-Si Field-Effect Transistors for High Voltage Power Applications
CMOS-compatible 100/650 V enhancement-mode FETs and 650 V depletion-mode MISFETs are fabricated on 6-inch AlGaN/GaN-on-Si wafers. They show high breakdown voltage and low specific on-resistance with good wafer uniformity. The importance of epitaxial quality is figured out in a key industrial item: high-temperature-reverse-bias-stress-induced on-state drain curent degradation. Optimization of epitaxial layers shows significant improvement of device reliability.
Germanium p-Channel FinFET Fabricated by aspect ratio trapping
We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at V DS =-0.5 V, good short-channel effect control, and high transconductance (g m =1.2 mS/μm at V DS =-1 V and 1.05 mS/μm at V DS =-0.5 V for L G =70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.
Electrical Characterization and Materials Stability Analysis of La2O3/HfO2 Composite Oxides on n-In0.53Ga0.47As MOS Capacitors With Different Annealing Temperatures
In this letter, a high-k composite oxide composed of La 2 O 3 and HfO 2 is investigated for n-In 0.53 Ga 0.47 As metal-oxide-semiconductor (MOS) capacitor application. The composite oxide was formed by depositing five layers of La 2 O 3 (0.8 nm)/HfO 2 (0.8 nm) on InGaAs with post deposition annealing at 500°C. The MOS capacitors fabricated show good inversion behavior, high capacitance, low leakage current, with excellent interface trap density (D it ) of 7.0×10 11 cm -2 eV -1 , small hysteresis of 200 mV and low capacitance equivalent thickness of 2.2 nm at 1 kHz were also achieved.
Electrostatics and ballistic transport studies in junctionless nanowire transistors
In this work a drift-diffusion simulator is utilized to study the electrostatics of a cylindrical gate-all-around junctionless nanowire transistor. For carrier transport properties such as carrier scattering and velocity in channel, a full band Monte Carlo is adopted to simulate non-equilibrium and ballistic behaviors. Two major cases: different S/D extension schemes and channel doping effects are examined in this study. It is observed that S/D extension underlap can benefit short-channel control and carrier velocity. In addition, channel doping is found to play an import role to increase carrier injection velocity in the junctionless nanowire transistors.
Quantum confinement point of view for mobility and stress responses on (100) and (110) SingleGate and double-gate nMOSFETs
Impact of quantum confinement on electron mobility and its stress responses for (100) and (110)-orientated single-gate (SG) and double-gate (DG) nMOSFETs is studied. Unstrained electron mobility in (110) DG nMOSFETs is found to be significantly higher than that of (110) SG devices. This paper discusses another physical explanation to the experimentally observed higher electron mobility in (110) FinFET sidewall channels as compared to that observed in planar (110) devices. It is also found that the electron mobility increases faster under uniaxial tensile stress for (110) devices than for (100) ones. The higher mobility in (110) DG devices is attributed to the lighter confinement effective mass of Δ4 valleys and the non-parabolicity of Δ2 valleys along the <;110> directions. With high enough tensile strain, DG nMOSFETs with (110) surface orientation are expected to outperform these on (100).
Mobility and screening effect in heavily doped accumulation-mode metal-oxide-semiconductor field-effect transistors
Measurements made on heavily doped n-channel accumulation-mode planar metal-oxide-semiconductor field-effect transistors (MOSFETs) reveal that the channel mobility can reach values significantly higher than the bulk mobility at the same doing level. This effect is attributed to a screening effect: in the accumulation channel, the high concentration of the majority carriers brings about an electrostatic screening effect that reduces impurity coulomb scattering. As a result, mobility values that can reach twice the value expected in the bulk material are observed in the accumulation channel.
Molecular Dynamic simulation study of stress memorization in Si dislocations
Stress-Memorization-Technique by Si dislocations is effective in enhancing NFET device performance [1,2]. For the first time, MD (Molecular Dynamic) simulations are applied to explain the formation mechanism of dislocations during the Solid-Phase-Epitaxy-Regrowth (SPER) process. A semi- empirical TCAD method based on lattice-KMC (L-KMC) is then developed to predict dislocation formation. The simulated dislocation positions agree well with silicon experiments characterized by TEM. TCAD simulations show that the resulting dislocations are along the [111] direction and provide ~650MPa average longitudinal stress in channel regions, consistent with Nano-Beam-Diffraction (NBD) strain measurement. The channel stress is predicted by simulation to further increase by 1.5X after the poly-silicon gate removal step in a replacement-gate process. The dislocation SMT enhances NFET electron mobility by 25% and Ion-Ioff performance by 15%.
28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications
An industry leading 28nm high-performance mobile SoC technology featuring metal-gate/high-k process is presented. The technology is optimized to offer wide power-to-performance transistor dynamic range and highest wired gate density with superior low-R/ELK interconnects, critical for next generation mobile computing/SOC applications. Through process and design optimization, historical trend is maintained for gate density and SRAM cell sizes. Variations control strategy through process and design collaboration is also described.
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
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