Logic

The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%.

An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process. it was found to gain additional /spl sim/10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process. which is a promising local strain approach for sub-65nm CMOS application.

Direct electro-deposition of a highly conformal and adherent Cu seed on ALD TaN by means of electro-grafting technique is presented. Both the adhesion of Cu seed to the underlying ALD TaN and EM lifetime performance were greatly enhanced by electro-grafting process, while the benefit of low via and line resistance of ALD TaN were maintained. This direct plated Cu seed layer on ALD TaN was demonstrated to successfully extend the current ECP to 45nm-node metallization and beyond.

Channel backscattering coefficients in the k/sub B/T layer (near the source) of 1.65-nm-thick gate oxide, 68-nm gate length bulk n-channel MOSFETs are systematically separated into two distinct components: the quasithermal-equilibrium mean-free-path for backscattering and the width of the k/sub B/T layer. Evidence to confirm the validity of the separation procedure is further produced: 1) the near-source channel conduction-band profile; 2) the existing value of k/sub B/T layer width from the sophisticated device simulation; and 3) an analytic temperature-dependent drain current model for the channel backscattering coefficients. The findings are also consistent with each other and therefore corroborate channel backscattering as the origin of the coefficients. Other interpretations and clarifications are determined with respect to the very recently released Monte Carlo particle simulation. Consequently, it can be reasonably claimed that the separated components, as well as their dependencies on temperature and bias, are adequate while being used to describe the operation of the devices undertaken within the framework of the channel backscattering theory.

The influence of preamorphization and solid-phase epitaxial regrowth on indium doping profile was discussed. Premorphised silicon significantly reduces channeling during indium ion implantation, producing a much more abrupt doping profile. It is suggested that during recrystallization by thermal annealing, indium segregates in front of the moving amorphous/crystalline interface, creating a clearly visible peak in the doping profile. It was also suggested that the indium segregation phenomenon get enhanced at lower temperatures.

A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.

Impact of shallow trench isolation (STI) induced mechanical stress on MOSFET drive current is investigated by means of a full-matrix active area layout experiment in advanced CMOS process technology. It turns out remarkably that transistor drive current density per unit width is not independent of the active area size, particularly along the direction of the channel current flow. Opposite sensitivities are observed between n- and p-MOSFETs with respect to lateral active area size. The role of gate placement inside the active area is also addressed. A statistical analysis scheme to find principal components is carried out as well.

Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to mixed-signal/radio-frequency (MS/RF) segments. Improvements in device speed, matching, and minimum noise figure are all consistent with fundamental scaling trends. Other figures-of-merit such as linearity and 1/f noise do not scale favorably but are not considered to be roadblocks when viewed from a circuit design perspective. Furthermore, interconnect architectural scaling trends in logic technology have facilitated improvements in passive-component performance metrics. These improvements compounded with innovations in circuit design have made CMOS technology the primary choice for cost driven MS/RF applications. This paper reviews active and passive elements of CMOS MS/RF system-on-chip (SoC) technology from a scaling perspective. The paper also discusses the implications that physical phenomena such as mechanical stress and gate leakage as well as gate patterning have on technology definition and characterization.

This paper discusses an integrated modeling approach for diffusion profiles in advanced CMOS technologies. First, for USJ (Ultra-Shallow Junction) arsenic modeling, in addition to a fully-coupled model with implant damage, amorphous layer formation which depends on the Frenkel pair concentration and evolution of (311) defects and dislocation loops based on EOR (End of Range) defects are also used. Secondly, in order to improve polysilicon activation, a hybrid (arsenic + phosphorus) Source/Drain is used for NMOS. We also address the calibration of the hybrid Source/Drain for with various anneal temperatures. It is shown that modeling of the hybrid Source/Drain profile can be achieved by optimization of the dopant's Fermi level dependent diffusivity and the initial value of the point defect concentration in the equilibrium state. Finally, uphill diffusion at low anneal temperature is observed for BF2 USJ and is enhanced with Ge pre-implants. It is caused by a steep interstitial gradient created by preamorphisation and EOR damage, ultra-shallow boron profile, and boron long-hop diffusion. A BIC (Boron-Interstitial Cluster) model is employed to model boron diffusion after a spike RTA at both extension and S/D regions.