Logic

A 1.4 nm EOT stack film of HfSiON with interfacial oxide layer (IL) is demonstrated with excellent electrical characteristics and reliability for 45 nm node low-power technology. Mobility comparable to SiON is achieved along with adequate nMOS PBTI lifetime, TDDB lifetime, and breakdown voltage (V BD ). For the first time, we report lower V BD for the HfSiON stack film despite of 3 orders gate leakage reduction compared to the same EOT SiON. It is attributed to IL breakdown in the proposed two-step breakdown mechanism. This possibly limits the scalability of such a stack film. On the other side, over-drivability of HfSiON with thick underlying oxide boosts input/output (I/O) device performance significantly

N-channel metal–oxide–semiconductor field effect transistors (MOSFETs) with a lightly doped well exhibit subthreshold current versus voltage (I–V) characteristics that are sensitive to shallow trench isolation (STI) mechanical stress. Such striking dependencies offer the opportunity to validate a proposed two-dimensional (2D) process model that relates the impurity diffusion to the mechanical stress throughout the substrate. With the assistance of sophisticated process/device simulations, the model appears to satisfactorily reproduce subthreshold I–V characteristics for different active area lengths and different substrate biases. The stress-dependent point defect equilibrium concentration and diffusion model are also implemented to evaluate the stress effect on transient enhanced diffusion.

A study was performed to investigate the effect of multiple stressors on CMOS devices on (110) and (100) substrates with different channel directions. For the first time, 87% I ON -I OFF improvement is achieved by utilizing SiGe-S/D and compressive contact etch stop layer (c-CESL) for PMOS devices on (110) substrate with lang111'rang channel direction. The improvement is similar to that on conventional (100) substrate with lang110>rangchannel direction and can be explained by piezoresistive coefficients. Record PMOS device performance of I on = 900 muA/mum at I off = 100 nA/mum and V DD = 1.0V for 40nm gate length is demonstrated

Optimizing nitrogen incorporation in HfSiON gate dielectric can improve overall reliability, e.g. nMOS PBTI lifetime, hot carrier (HC) lifetime, time-to-breakdown (tBD), without adverse effects on pMOS NBT1 lifetime and electron/hole mobility. The improvement is attributed to excellent thermal stability against partial-crystallization after 1100/spl deg/C annealing, and the concomitantly reduced trap generation minimizes stress induced leakage current (SILC) and flicker noise degradation after PBTI stress. A new methodology is proposed, for the first time, to correctly predict HC lifetime of HfSiON nMOS based on electron trapping.

The effect of shallow trench isolation mechanical stress on MOSFET dopant diffusion has become significant, and affects device behavior for sub-100-nm technologies. This paper presents a stress-dependent dopant diffusion model and demonstrates its capability to reflect experimental results for a state-of-the-art logic CMOS technology. The proposed stress-dependent dopant diffusion model is shown to successfully reproduce device characteristics covering a wide range of active area sizes, gate lengths, and device operating conditions.

The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%.

An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process. it was found to gain additional /spl sim/10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process. which is a promising local strain approach for sub-65nm CMOS application.

Direct electro-deposition of a highly conformal and adherent Cu seed on ALD TaN by means of electro-grafting technique is presented. Both the adhesion of Cu seed to the underlying ALD TaN and EM lifetime performance were greatly enhanced by electro-grafting process, while the benefit of low via and line resistance of ALD TaN were maintained. This direct plated Cu seed layer on ALD TaN was demonstrated to successfully extend the current ECP to 45nm-node metallization and beyond.

Channel backscattering coefficients in the k/sub B/T layer (near the source) of 1.65-nm-thick gate oxide, 68-nm gate length bulk n-channel MOSFETs are systematically separated into two distinct components: the quasithermal-equilibrium mean-free-path for backscattering and the width of the k/sub B/T layer. Evidence to confirm the validity of the separation procedure is further produced: 1) the near-source channel conduction-band profile; 2) the existing value of k/sub B/T layer width from the sophisticated device simulation; and 3) an analytic temperature-dependent drain current model for the channel backscattering coefficients. The findings are also consistent with each other and therefore corroborate channel backscattering as the origin of the coefficients. Other interpretations and clarifications are determined with respect to the very recently released Monte Carlo particle simulation. Consequently, it can be reasonably claimed that the separated components, as well as their dependencies on temperature and bias, are adequate while being used to describe the operation of the devices undertaken within the framework of the channel backscattering theory.