Mobility enhancement and strain integration in advanced CMOS
Mobility enhancement techniques have become pervasive in advanced CMOS technologies. Non-scalable and scalable approaches to mobility enhancement are widely used in various application segments (high-speed, low-operating power, and low- standby power). Non-scalable techniques rely on preferential channel directions having fundamentally higher carrier mobility than the conventional <110> directions of (100) substrates. On the other hand, scalable techniques rely on process built-in mechanical strain to boost mobility as a result of band- structure response impacting both carrier-effective mass and scattering rates. Scalable techniques are based on the channel strain induced by contact-etch stop layers or Si(1-x)Ge(x) structures primarily. This paper will review both non-scalable and scalable mobility enhancement approaches from two angles, namely fundamental device physics and overall device integration schemes. The paper will also review and discuss issues related to superposition of process built-in strain for performance enhancement.
A new series resistance and mobility extraction method by BSIM model for nano-scale MOSFETs
In this work, a simplified BSIM-based model has been proposed to solve the above issues contributed by halo implants [Goto, K, et al., 2003]. In this new methodology, R sd and mu eff can be uniquely extracted in nano-scale devices. Furthermore, the extracted L G dependency of mu eff may serve as a good indicator for monitoring the relationship between geometry and stress parameters
HfSiON gate dielectric for 45nm node low-power device
A 1.4 nm EOT stack film of HfSiON with interfacial oxide layer (IL) is demonstrated with excellent electrical characteristics and reliability for 45 nm node low-power technology. Mobility comparable to SiON is achieved along with adequate nMOS PBTI lifetime, TDDB lifetime, and breakdown voltage (V BD ). For the first time, we report lower V BD for the HfSiON stack film despite of 3 orders gate leakage reduction compared to the same EOT SiON. It is attributed to IL breakdown in the proposed two-step breakdown mechanism. This possibly limits the scalability of such a stack film. On the other side, over-drivability of HfSiON with thick underlying oxide boosts input/output (I/O) device performance significantly
Reproducing subthreshold characteristics of metal-oxide-semiconductor field effect transistors under shallow trench isolation mechanical stress using a stress-dependent diffusion model
N-channel metal–oxide–semiconductor field effect transistors (MOSFETs) with a lightly doped well exhibit subthreshold current versus voltage (I–V) characteristics that are sensitive to shallow trench isolation (STI) mechanical stress. Such striking dependencies offer the opportunity to validate a proposed two-dimensional (2D) process model that relates the impurity diffusion to the mechanical stress throughout the substrate. With the assistance of sophisticated process/device simulations, the model appears to satisfactorily reproduce subthreshold I–V characteristics for different active area lengths and different substrate biases. The stress-dependent point defect equilibrium concentration and diffusion model are also implemented to evaluate the stress effect on transient enhanced diffusion.
High-Performance PMOS Devices on (110)/<111'> Substrate/Channel with Multiple Stressors
A study was performed to investigate the effect of multiple stressors on CMOS devices on (110) and (100) substrates with different channel directions. For the first time, 87% I ON -I OFF improvement is achieved by utilizing SiGe-S/D and compressive contact etch stop layer (c-CESL) for PMOS devices on (110) substrate with lang111'rang channel direction. The improvement is similar to that on conventional (100) substrate with lang110>rangchannel direction and can be explained by piezoresistive coefficients. Record PMOS device performance of I on = 900 muA/mum at I off = 100 nA/mum and V DD = 1.0V for 40nm gate length is demonstrated
Reliability of HfSiON as gate dielectric for advanced CMOS technology
Optimizing nitrogen incorporation in HfSiON gate dielectric can improve overall reliability, e.g. nMOS PBTI lifetime, hot carrier (HC) lifetime, time-to-breakdown (tBD), without adverse effects on pMOS NBT1 lifetime and electron/hole mobility. The improvement is attributed to excellent thermal stability against partial-crystallization after 1100/spl deg/C annealing, and the concomitantly reduced trap generation minimizes stress induced leakage current (SILC) and flicker noise degradation after PBTI stress. A new methodology is proposed, for the first time, to correctly predict HC lifetime of HfSiON nMOS based on electron trapping.
Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs
The effect of shallow trench isolation mechanical stress on MOSFET dopant diffusion has become significant, and affects device behavior for sub-100-nm technologies. This paper presents a stress-dependent dopant diffusion model and demonstrates its capability to reflect experimental results for a state-of-the-art logic CMOS technology. The proposed stress-dependent dopant diffusion model is shown to successfully reproduce device characteristics covering a wide range of active area sizes, gate lengths, and device operating conditions.
45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell
The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.
65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application
This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%.
Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application
An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process. it was found to gain additional /spl sim/10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process. which is a promising local strain approach for sub-65nm CMOS application.
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
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