Logic

CMOS technology scaling has come to a point whereby traditional assumptions that warranted a fair degree of de-coupling between process development and circuit/system design do not hold. One specific example relates to chip standby leakage. Today's most advanced transistor designs push gate dielectric thickness into a regime where direct tunneling currents are no longer negligible. Meanwhile, the portable electronics sector had become a key industry driver demanding VLSI circuits with ever increasing functionality-performance needs while maintaining tight controls on power consumption. To conciliate the scaling-driven technology fundamental limitations with the industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize Systems on a Chip (SoC). This paper discusses aspects of bulk CMOS SoC technology definition and front-end scaling trends.

This paper introduces new technology features to support ultra high-speed and MS/RF applications incorporated into a leading-edge fully manufacturable 0.13 /spl mu/m CMOS foundry technology (K.K. Young et al, IEDM Tech Digest, pp. 563-566, 2000). New core devices with 15.5 /spl Aring/ and nominal 75 nm physical gate lengths support at least 10% performance improvement with respect to prior release. These devices offer the best I/sub off/-I/sub dsat/ performance reported so far for 1.2 V applications. To support high-speed I/O standards, additional 1.8 V-32 /spl Aring/ I/O devices are integrated with the 15.5 /spl Aring/ transistors. Leading-edge passive elements for MS/RF applications are reported in this work. Advanced Cu/low-k back end process integration that can support up to nine layers of metal is also demonstrated.

Optimization of a LDD doping profile to enhance hot carrier resistance in 3.3 V input/output CMOS devices has been performed by utilizing phosphorus transient enhanced diffusion (TED). Hot carrier effects in hybrid arsenic/phosphorus LDD nMOSFET's with and without TED are characterized comprehensively. Our result shows that the substrate current in a nMOSFET with phosphorus TED can be substantially reduced, as compared to the one without TED. The reason is that the TED effect can yield a more graded n/sup -/ LDD doping profile and thus a smaller lateral electric field. Further improvement of hot carrier reliability can be achieved by optimizing arsenic implant energy. Secondary ion mass spectrometry analysis for TED effect and two-dimensional (2-D) device simulation for electric field and current flow distributions have been conducted. The phosphorus TED effects on transistor driving current and off-state leakage current are also investigated.

In this paper, we demonstrate the effects of CMOS technology scaling on the high temperature characteristics (from 25/spl deg/C to 125/spl deg/C) of the four components of off-state drain leakage (I/sub off/) (i.e. subthreshold leakage (I/sub sub/), gate edge-direct-tunneling leakage (I/sub EDT/), gate-induced drain-leakage (I/sub GIDL/), and bulk band-to-band-tunneling leakage (I/sub B-BTBT/)). In addition, the high temperature characteristics of I/sub off/ with reverse body bias (V/sub B/) for the further reduction of the standby leakage are also demonstrated. The discussion is based on the data measured from three CMOS logic technologies (i.e., low-voltage and high performance (LV), low-power (LP), and ultra-low-power (ULP)) and three generations (0.18 /spl mu/m, 0.15 /spl mu/m, and 0.13 /spl mu/m). Experiments show that the optimum V/sub B/, which minimizes I/sub off/, is a function of temperature. The experiments also show that for CMOS logic technologies of the next generations, it is important to control I/sub B-BTBT/ and I/sub GIDL/ by reducing effective doping concentration and doping gradient. It seems that in order to conform on-state gate leakage (I/sub G-on/) and I/sub EDT/ specifications and to retain a 10-20% performance improvement at the same time, it is indispensable to use high-quality and high-dielectric-constant materials to reduce effective oxide thickness (EOT). The role of each leakage component in SRAM standby current (I/sub SB/) is also analyzed.

This paper describes a leading-edge 0.13 /spl mu/m low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I/sub off/) and gate delay (T/sub d/) performance at operating voltages (V/sub cc/) of 1.5 V and 1.2 V, devices with 0.11 /spl mu/m nominal gate length (L/sub g-nom/) and various gate-oxide thicknesses (T/sub ox/) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 /spl Aring/ in order to keep acceptable off-state power consumption at V/sub cc/=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T/sub ox/=26 /spl Aring/) is targeted for V/sub cc/=1.5 V with worst case I/sub off/ <10 pA//spl mu/m and nominal gate delay 24 ps/gate. Another design, named LP1 (T/sub ox/=22 /spl Aring/) is targeted for V/sub cc/=1.2 V with worst case I/sub off/<20 pA//spl mu/m and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 /spl mu/A//spl mu/m nominal drive currents at V/sub cc/ for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 /spl mu/m/sup 2/ cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T/sub ox/=22 /spl Aring/) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125/spl deg/C and V/sub cc/=1.5 V.

We discuss the 1D/2D modeling of arsenic profiles under soak and spike anneal conditions at both shallow extension and high concentration source/drain areas. This work also addresses the calibration of the phosphorus profile in a hybrid (arsenic + phosphorus) source/drain with various anneal temperatures. It is shown that the "+1" or modified "+n" model is not necessary for shallow arsenic profile modeling under spike anneal conditions. Finally, it is also shown that modeling of the hybrid source/drain profile can be achieved by optimization of the dopant's Fermi level dependent diffusivity, initial value of point defects concentration at equilibrium state, and neglect of implant induced damage.

A leading edge 90nm bulk CMOS device technology is described in this paper. In this technology, multi Vt and multi gate oxide devices are offered to support low standby power (LP), general-purpose (G or ASIC), and high-speed (HS) system on chip (SoC) applications. High voltage I/O devices are supported using 70/spl Aring/, 50/spl Aring/, and 28/spl Aring/ gate oxide for 3.3V, 2.5V, and 1.5-1.8V interfaces, respectively. The backend architecture is based on nine levels of Cu interconnect with hot black diamond (HBD) low-k dielectric (k<=3.0).

The ratio of the mean-free-path to the critical length near the low-field source is key to channel backscattering characteristics in nanoFETs. To extract it, we perform temperature experiment from -40/spl deg/C to 75/spl deg/C on 17 /spl Aring/ thick gate oxide MOSFETs with varying mask gate lengths down to 75 nm. In this paper we report that once the saturation drain current is measured against temperature, the mean-free-path /spl lambda/ with respect to the critical length l can readily be assessed at specific temperature. Dependencies on gate length, drain voltage, and gate voltage are then established that further enable nanoFETs scaling projections. The temperature dependent version of existing backscattering model is derived in this work.

This letter introduces an analytical model to represent line-edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices. The model partitions a given device into small unit cells along its width, each unit cell assumes a constant gate length (i.e., cell's width is small compared to LER spatial frequency). An analytical model is used to represent saturated threshold voltage dependency on the unit cell's gate length. Using this technique, an efficient and accurate model for LER effects (through V/sub ts/ variations) on off-state leakage and drive current is proposed and experimentally validated using 193 and 248 nm lithography for devices with 80-nm nominal gate lengths. Assuming that the deviation from the ideal 0-LER case remains constant from generation to generation, the model predicts that 3 nm or less LER is required for 50-60-nm state-of-the-art devices in the 0.1-μm technology node. Based on data presented, we suggest that the LER requirement for this technology node is attainable with an alternated phase-shift type of patterning process.

The characteristics of polysilicon resistors in sub-0.25 μm CMOS ULSI applications have been studied. Based on the presented sub-0.25 μm CMOS borderless contact, both n/sup +/ and p/sup +/ polysilicon resistors with Ti- and Co-salicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate the essential parameters of polysilicon resistors including electrical delta W(/spl Delta/W), interface resistance R/sub interface/, and pure sheet resistance R/sub pure/. This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-0.25 μm CMOS technology.