Logic

Direct electro-deposition of a highly conformal and adherent Cu seed on ALD TaN by means of electro-grafting technique is presented. Both the adhesion of Cu seed to the underlying ALD TaN and EM lifetime performance were greatly enhanced by electro-grafting process, while the benefit of low via and line resistance of ALD TaN were maintained. This direct plated Cu seed layer on ALD TaN was demonstrated to successfully extend the current ECP to 45nm-node metallization and beyond.

Channel backscattering coefficients in the k/sub B/T layer (near the source) of 1.65-nm-thick gate oxide, 68-nm gate length bulk n-channel MOSFETs are systematically separated into two distinct components: the quasithermal-equilibrium mean-free-path for backscattering and the width of the k/sub B/T layer. Evidence to confirm the validity of the separation procedure is further produced: 1) the near-source channel conduction-band profile; 2) the existing value of k/sub B/T layer width from the sophisticated device simulation; and 3) an analytic temperature-dependent drain current model for the channel backscattering coefficients. The findings are also consistent with each other and therefore corroborate channel backscattering as the origin of the coefficients. Other interpretations and clarifications are determined with respect to the very recently released Monte Carlo particle simulation. Consequently, it can be reasonably claimed that the separated components, as well as their dependencies on temperature and bias, are adequate while being used to describe the operation of the devices undertaken within the framework of the channel backscattering theory.

The influence of preamorphization and solid-phase epitaxial regrowth on indium doping profile was discussed. Premorphised silicon significantly reduces channeling during indium ion implantation, producing a much more abrupt doping profile. It is suggested that during recrystallization by thermal annealing, indium segregates in front of the moving amorphous/crystalline interface, creating a clearly visible peak in the doping profile. It was also suggested that the indium segregation phenomenon get enhanced at lower temperatures.

A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.

Impact of shallow trench isolation (STI) induced mechanical stress on MOSFET drive current is investigated by means of a full-matrix active area layout experiment in advanced CMOS process technology. It turns out remarkably that transistor drive current density per unit width is not independent of the active area size, particularly along the direction of the channel current flow. Opposite sensitivities are observed between n- and p-MOSFETs with respect to lateral active area size. The role of gate placement inside the active area is also addressed. A statistical analysis scheme to find principal components is carried out as well.

This paper discusses an integrated modeling approach for diffusion profiles in advanced CMOS technologies. First, for USJ (Ultra-Shallow Junction) arsenic modeling, in addition to a fully-coupled model with implant damage, amorphous layer formation which depends on the Frenkel pair concentration and evolution of (311) defects and dislocation loops based on EOR (End of Range) defects are also used. Secondly, in order to improve polysilicon activation, a hybrid (arsenic + phosphorus) Source/Drain is used for NMOS. We also address the calibration of the hybrid Source/Drain for with various anneal temperatures. It is shown that modeling of the hybrid Source/Drain profile can be achieved by optimization of the dopant's Fermi level dependent diffusivity and the initial value of the point defect concentration in the equilibrium state. Finally, uphill diffusion at low anneal temperature is observed for BF2 USJ and is enhanced with Ge pre-implants. It is caused by a steep interstitial gradient created by preamorphisation and EOR damage, ultra-shallow boron profile, and boron long-hop diffusion. A BIC (Boron-Interstitial Cluster) model is employed to model boron diffusion after a spike RTA at both extension and S/D regions.

Intensive experiment on highly scaled MOSFETs with mask gate lengths down to 90 nm shows significant sensitivities (up to 10%) of drive current per unit width to the shrinking of active area size down to 0.6 /spl mu/m as well as to the gate placement distance from STI (shallow trench isolation) edge. This suggests the impact of STI induced mechanical stress along the direction of the channel current flow. Even n-and p-channel FETs are observed to behave in opposite trends with respect to the lateral active area size. Mechanical stress simulation of underlying entire front-end process line is conducted also intensively. Systematic analysis turns out strikingly that the experimental drive current sensitivity tracks well the compressive-type strain along the channel, leading to a correlation established between the two. This work promises exploration of mechanical stress issues in future nanoscale devices and circuits.

This paper demonstrates a new compact and scaleable model of mechanical stress effects on MOS electrical performance, induced by shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.