Logic

Low resistance contact technology for 2D semiconductors is a key bottleneck for the practical application of 2D channel materials at advanced logic nodes. This work presents a novel Sb-Pt modulated contact technology which can alleviate the Fermi-level pinning effect and mediate the band alignment at the metal-2D semiconductor interface, leading to exceptional ohmic contacts for both p-type and n-type WSe 2 FETs (p/n FET). WSe 2 FETs with different Sb/Pt contact compositions, in combination with new oxide-based encapsulation/doping technologies, exhibits record low pFET contact resistance of 0.75kΩ∙μm among all reported monolayer (1L) 2D pFETs. The nFET contact resistance of 1.8kΩ∙μm is also the lowest among 1L WSe 2 nFETs. Both 1L WSe 2 pFET and nFET demonstrated remarkable on-state p/n current ∼150μA/μm at |V_D|=1V, indicating the potential of WSe 2 for CMOS applications. A new version of the semi-automated dry transfer process for chemical vapor deposition (CVD) WSe 2 was also developed utilizing a novel Bi/PMMA/TRT support stack, offering low defect wrinkle-free WSe 2 transfer at wafer-scale.

Transistor scaling enabled by gate length scaling requires EOT scaling to less than 1 nm thickness [1]. This work successfully integrates Hf-based ALD higher-k dielectrics with CVD-grown monolayer (1L) MoS 2 to build top-gate nFET with EOT ~1 nm with nearly ideal subthreshold swing of 68 mV/dec. The gate stack described here achieves a high ε_eff ~13.53, a large E_BD ~12.4MV/cm, and excellent leakage current density. This is a remarkable performance among reported gate dielectrics on the transition metal dichalcogenides (TMDs) on which it is notoriously difficult to deposit a pinhole-free dielectric.

We present the first demonstration of p-MOSFET with a high ON current of 10⁻⁵A/um and good S.S. ∼80mV/dec. MOSFETs have the advantage of lower access resistance compared to Schottky barrier FETs. This requires spacer doping. Here, we introduce a self-limiting, fab-compatible process which consists of WO_x obtained from WSe₂ by O 2 plasma conversion. We analyze the process condition which enhance the doping effect. We quantify the doping level and the impact of the channel bandgap. We demonstrate a self-aligned version of the spacer doping for MOSFET fabrication.

Low-dimensional materials (LDMs) such as two-dimensional transition metal dichalcogenides (2D TMDs) and carbon nanotubes (CNTs) have the potential to be the channel material in extremely scaled CMOS transistors. Based on current hardware data, the design space for contacted-gate pitch (CGP) scaled transistors is explored for these materials. The ON current, sources of leakage which limit OFF current, and CGP scaling potential are analyzed by separately considering effects from shrinking the gate length, contact length, and extension length. Doping of LDM is the main challenge to reduce contact and extension resistance for scaled transistors. Experimental control of p-type doping of 2D is reported as an example of doping impact.

A novel wafer-scale semi-automated dry transfer process for monolayer (1L) CVD WS 2 was developed utilizing the weakly coupled interface between semimetal (Bi) and two-dimensional (2D) semiconductor (WS 2 ). Bi semimetal serves as a gently adhesive transfer template for 2D materials, introducing minimal additional defects during the transfer process. Based on 2D materials processed using this new transfer method, semimetal-contacted (Bi and Sb) monolayer CVD WS 2 nFETs were further demonstrated at wafer scale. Our CVD 1L WS 2 nFETs fabricated using semimetal-assisted transfer with semimetal (Bi and Sb) contacts show record high on-current of 250 µA/µm and 243 µA/µm at V DS = 1 V, and record low contact resistance of 0.63 kΩ•µm and 0.73 kΩ•µm, respectively.

Advanced beyond-silicon electronic technology requires both channel materials and also ultralow-resistance contacts to be discovered. Atomically thin two-dimensional semiconductors have great potential for realizing high-performance electronic devices. However, owing to metal-induced gap states (MIGS), energy barriers at the metal–semiconductor interface—which fundamentally lead to high contact resistance and poor current-delivery capability—have constrained the improvement of two-dimensional semiconductor transistors so far. Here we report ohmic contact between semimetallic bismuth and semiconducting monolayer transition metal dichalcogenides (TMDs) where the MIGS are sufficiently suppressed and degenerate states in the TMD are spontaneously formed in contact with bismuth. Through this approach, we achieve zero Schottky barrier height, a contact resistance of 123 ohm micrometres and an on-state current density of 1,135 microamps per micrometre on monolayer MoS2; these two values are, to the best of our knowledge, the lowest and highest yet recorded, respectively. We also demonstrate that excellent ohmic contacts can be formed on various monolayer semiconductors, including MoS2, WS2 and WSe2. Our reported contact resistances are a substantial improvement for two-dimensional semiconductors, and approach the quantum limit. This technology unveils the potential of high-performance monolayer transistors that are on par with state-of-the-art three-dimensional semiconductors, enabling further device downscaling and extending Moore’s law.

Ultrathin two-dimensional (2D) semiconducting layered materials offer great potential for extending Moore’s law of the number of transistors in an integrated circuit1. One key challenge with 2D semiconductors is to avoid the formation of charge scattering and trap sites from adjacent dielectrics. An insulating van der Waals layer of hexagonal boron nitride (hBN) provides an excellent interface dielectric, efficiently reducing charge scattering2,3. Recent studies have shown the growth of single-crystal hBN films on molten gold surfaces4 or bulk copper foils5. However, the use of molten gold is not favoured by industry, owing to its high cost, cross-contamination and potential issues of process control and scalability. Copper foils might be suitable for roll-to-roll processes, but are unlikely to be compatible with advanced microelectronic fabrication on wafers. Thus, a reliable way of growing single-crystal hBN films directly on wafers would contribute to the broad adoption of 2D layered materials in industry. Previous attempts to grow hBN monolayers on Cu (111) metals have failed to achieve mono-orientation, resulting in unwanted grain boundaries when the layers merge into films6,7. Growing single-crystal hBN on such high-symmetry surface planes as Cu (111)5,8 is widely believed to be impossible, even in theory. Nonetheless, here we report the successful epitaxial growth of single-crystal hBN monolayers on a Cu (111) thin film across a two-inch c-plane sapphire wafer. This surprising result is corroborated by our first-principles calculations, suggesting that the epitaxial growth is enhanced by lateral docking of hBN to Cu (111) steps, ensuring the mono-orientation of hBN monolayers. The obtained single-crystal hBN, incorporated as an interface layer between molybdenum disulfide and hafnium dioxide in a bottom-gate configuration, enhanced the electrical performance of transistors. This reliable approach to producing wafer-scale single-crystal hBN paves the way to future 2D electronics.

High performance carbon nanotube (CNT) network transistors with on-resistance (R on ) of <; 250 Ω are successfully integrated as back-end-of-the-line (BEOL) power gating devices onto Si CMOS wafers manufactured using 28-nm process technology. When the power supply is connected through the BEOL CNT network header array, the front-end-of-the-line (FEOL) Si ring oscillators (ROs) achieve a similar quiescent current (I DDQ ) and have the comparable active power (P ACTIVE ) consumption under the same operation frequency as compared to the operation without the power gating CNT transistors. The fabrication of CNT devices in the BEOL is verified to cause no performance degradation in the underlying FEOL Si CMOS devices. This study has successfully demonstrated heterogeneous integration of advanced Si logic circuits with low-cost and high-mobility CNT transistors in the BEOL fabricated at low, BEOL-compatible temperatures (250 °C).

For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS 2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS 2 channels on SiO x /Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10 6 , a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).