Logic

CMOS-compatible 100/650 V enhancement-mode FETs and 650 V depletion-mode MISFETs are fabricated on 6-inch AlGaN/GaN-on-Si wafers. They show high breakdown voltage and low specific on-resistance with good wafer uniformity. The importance of epitaxial quality is figured out in a key industrial item: high-temperature-reverse-bias-stress-induced on-state drain curent degradation. Optimization of epitaxial layers shows significant improvement of device reliability.

We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at V DS =-0.5 V, good short-channel effect control, and high transconductance (g m =1.2 mS/μm at V DS =-1 V and 1.05 mS/μm at V DS =-0.5 V for L G =70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.

In this paper, a realistic atomic model is used to study the atomic ordering effect on electronic structures of Si 0.5 Ge 0.5 . The hybrid density functional theory (DFT), HSE06, is chosen as the methodology. The calculated bandgap and effective masses of Si and Ge at various symmetry points are first validated by the reported experimental data and empirical pseudo-potential method (EPM) calculations. The study of two different Si 0.5 Ge 0.5 atomic configurations shows that the SiSi-GeGe case is more stable than SiGe-SiGe (RS2 structure). In addition, the electron effective masses of the former one are larger than those of the latter one, and those calculated by EPM with virtual crystal approximation (VCA). This large electron effective mass is attributed to the localized electron orbital of the lowest anti-bonding state in the SiSi-GeGe case which leads to a flat E-k curve. However, no obvious ordering effect on hole effective mass is found.

High-k/InAs interfaces have been manufactured using InAs surface oxygen termination and low temperature atomic layer deposition of HfO2. Capacitance–voltage (C–V) curves revert to essentially classical shape revealing mobile carrier response in accumulation and depletion, hole inversion is observed, and predicted minority carrier response frequency in the hundred kHz range is experimentally confirmed; reference samples using conventional techniques show a trap dominated capacitance response. C–V curves have been fitted using advanced models including nonparabolicity and Fermi-Dirac distribution. For an equivalent oxide thickness of 1.3 nm, an interface state density Dit = 2.2 × 1011 cm−2 eV−1 has been obtained throughout the InAs bandgap. The authors would like to thank Y. C. Sun of TSMC and L. Samuelson of Lund University for their support.

In this letter, a high-k composite oxide composed of La 2 O 3 and HfO 2 is investigated for n-In 0.53 Ga 0.47 As metal-oxide-semiconductor (MOS) capacitor application. The composite oxide was formed by depositing five layers of La 2 O 3 (0.8 nm)/HfO 2 (0.8 nm) on InGaAs with post deposition annealing at 500°C. The MOS capacitors fabricated show good inversion behavior, high capacitance, low leakage current, with excellent interface trap density (D it ) of 7.0×10 11 cm -2 eV -1 , small hysteresis of 200 mV and low capacitance equivalent thickness of 2.2 nm at 1 kHz were also achieved.

Record setting III-V MOSFETs are reported. For the first time performance better than state-of-the-art HEMTs is demonstrated. For a MOSFET with 10 nm unstrained InAs surface channel and L g = 130 nm operating at 0.5 V, on-current as high as I on = 601 μA/μm (at fixed I off = 100 nA/μm) is achieved. This record performance is enabled by g m, ext = 2.72 mS/μm and S = 85 mV/dec, DIBL = 40 mV/V, resulting from breakthroughs in epitaxy and III-V/dielectric interface engineering. Measured mobility is 7100 cm 2 /V.s at n s = 6.7×10 12 cm -2 . Device simulations further elucidate the performance potential of III-V N-MOSFETs.

We demonstrate scaled, replacement gate high-k/metal gate p-channel Ge FinFETs integrated onto 300mm Si wafers for which the best device shows record peak g m, ext =2.7mS/μm (g m, int =3.3mS/μm), Q (≡g m, ext /SS sat ) = 32.4 and I on = 497μA/μm at I off = 100nA/μm, all at V ds = -0.5V. The high performance is a result of successful integration of <;110> oriented, highly scaled Ge fins on silicon substrates and of a low D it gate stack with capacitance equivalent thickness=8Å. This optimized gate stack supports the highest hole mobility ever reported at sub-10Å CET. Furthermore, Ge FinFETs in the present work outperform any other reported Ge devices by more than ~2.5× (g m /SS metric) and ~2× (I on /I off metric) at shortest gate lengths (down to 20nm) to the best of our knowledge.

The characteristics of Al2O3/InSb MOSCAPs processed with different postdeposition annealing (PDA) temperatures are investigated. X-ray photoelectron spectroscopy analysis shows a significant reduction of InSb-oxides after HCl plus trimethyl aluminum treatment and oxide deposition. Multifrequency capacitance-voltage (C–V) characteristics exhibit low-frequency and asymmetrical C–V behaviors, in which capacitance in the InSb conduction band side is lower than in the valence band side. The electrical properties of the MOSCAPs are sensitive to PDA temperature and degraded significantly at PDA temperature > 300 °C. This degradation is closely related to the diffusion of In, Sb into Al2O3 as indicated by transmission electron microscopy analyses.

In this work a drift-diffusion simulator is utilized to study the electrostatics of a cylindrical gate-all-around junctionless nanowire transistor. For carrier transport properties such as carrier scattering and velocity in channel, a full band Monte Carlo is adopted to simulate non-equilibrium and ballistic behaviors. Two major cases: different S/D extension schemes and channel doping effects are examined in this study. It is observed that S/D extension underlap can benefit short-channel control and carrier velocity. In addition, channel doping is found to play an import role to increase carrier injection velocity in the junctionless nanowire transistors.

Impact of quantum confinement on electron mobility and its stress responses for (100) and (110)-orientated single-gate (SG) and double-gate (DG) nMOSFETs is studied. Unstrained electron mobility in (110) DG nMOSFETs is found to be significantly higher than that of (110) SG devices. This paper discusses another physical explanation to the experimentally observed higher electron mobility in (110) FinFET sidewall channels as compared to that observed in planar (110) devices. It is also found that the electron mobility increases faster under uniaxial tensile stress for (110) devices than for (100) ones. The higher mobility in (110) DG devices is attributed to the lighter confinement effective mass of Δ4 valleys and the non-parabolicity of Δ2 valleys along the <;110> directions. With high enough tensile strain, DG nMOSFETs with (110) surface orientation are expected to outperform these on (100).