Logic

The ab initio work quantitatively explains the physical mechanism of threshold voltage shifts in n-type and p-type metal-oxide-semiconductor field-effect transistors with HfO 2 /Al 2 O 3 gate stack. In the study, the θ phase alumina has been chosen for better lattice matching of the (100) HfO 2 and (100) Si substrate. Using dipole correction method, the dominant dipole moment responsible for the threshold voltage shift has been identified at the interface of HfO 2 /Al 2 O 3 . Our HfO 2 /Al 2 O 3 atomic model shows the dipole moment decreases almost linearly as the alumina thickness decreases from four monolayers (13 Å) to one monolayer (3 Å). On account of the effects of capacitance and the dipole moment, our ab initio calculation quantitatively explains the trend and sensitivity of experimental threshold voltage shifts on n- and p-MOSFET's.

Two high-k dielectric materials (Al2O3 and HfO2) were deposited on n-type (100) and (110) InAs surface orientations to investigate physical properties of the oxide/semiconductor interfaces and the interface trap density (Dit). X-ray photoelectron spectroscopy analyses (XPS) for native oxides of (100) and (110) as-grown n-InAs epi wafers show an increase in As-oxide on the (100) surface and an increase in InOx on the (110) surface. In addition, XPS analyses of high-k (Al2O3 and HfO2) on n-InAs epi show that the intrinsic native oxide difference between (100) and (110) epi surfaces were eliminated by applying conventional in-situ pre-treatment (TriMethyAluminium (TMA)) before the high-k deposition. The capacitance-voltage (C-V) characterization of HfO2 and Al2O3 MOSCAPs on both types of n-InAs surfaces shows very similar C-V curves. The interface trap density (Dit) profiles show Dit minima of 6.1 × 1012/6.5 × 1012 and 6.6 × 1012/7.3 × 1012 cm−2 eV−1 for Al2O3 and HfO2, respectively for (100) and (110) InAs surfaces. The similar interface trap density (Dit) on (100) and (110) surface orientation were observed, which is beneficial to future InAs FinFET device with both (100) and (110) surface channel orientations present.

A low interface trap density (Dit) Al2O3/In0.53Ga0.47As/Si MOS capacitor fabricated on an In0.53Ga0.47As heterostructure layer directly grown on a 300 mm on-axis Si(100) substrate by MOCVD with a very thin buffer layer is demonstrated. Compared with the MOS capacitors fabricated on the In0.53Ga0.47As layer grown on the lattice-matched InP substrate, the Al2O3/In0.53Ga0.47As MOS capacitors fabricated on the Si substrate exhibit excellent capacitance–voltage characteristics with a small frequency dispersion of approximately 2.5%/decade and a low interface trap density Dit close to 5.5 × 1011 cm−2 eV−1. The results indicate the potential of integrating high-mobility InGaAs-based materials on a 300 mm Si wafer for post-CMOS device application in the future.

One of the major challenges of high mobility complementary metal-oxide-semiconductor (CMOS) circuits is to meet off-current requirements of <100 pA/μm for low stand-by power (LSTP) operation due to the small bandgap (≤0.5 eV) of the channel material (bandgap limit). In this work, we present experimental proof that the bandgap limit can be overcome at nanometer dimensions leveraging the phenomenon of steady state deep depletion (SSDD). The occurrence of SSDD is investigated using high-k capacitors with 5 and 10 nm InAs channel on a n- or p-type doped lattice matched wide bandgap AlAsSb layer. Absence of charge carriers at the off-state band edge is observed for 5 nm InAs channel layers demonstrating occurrence of SSDD and lifting of the off-state bandgap limit providing a path to meet LSTP requirements for future high mobility CMOS. The authors would like to thank the Nano Lab at Lund University for manufacturing assistance and Y. C. Sun of TSMC for support.

Electrical interface quality of various high- k dielectrics on GaSb, including Al 2 O 3 , HfO 2 , LaAlO 3 , GdScO 3 , and HfO 2 /Ga 2 O 3 bilayer has been studied and compared with reference low (AlGaSb) and high D it (native oxide) interfaces using photoluminescence intensity measurements for the first time. Al 2 O 3 and HfO 2 /Ga 2 O 3 bilayer dielectrics are identified with the lowest interface recombination velocity (S=7×10 4 cm/s) and consequently D it integrated across essentially the entire bandgap. However, S for even the best identified high- k dielectrics is elevated by 140× over the low D it AlGaSb reference indicating the need of further improvements for envisioned use in Sb based MOSFETs.

CMOS-compatible 100/650 V enhancement-mode FETs and 650 V depletion-mode MISFETs are fabricated on 6-inch AlGaN/GaN-on-Si wafers. They show high breakdown voltage and low specific on-resistance with good wafer uniformity. The importance of epitaxial quality is figured out in a key industrial item: high-temperature-reverse-bias-stress-induced on-state drain curent degradation. Optimization of epitaxial layers shows significant improvement of device reliability.

We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at V DS =-0.5 V, good short-channel effect control, and high transconductance (g m =1.2 mS/μm at V DS =-1 V and 1.05 mS/μm at V DS =-0.5 V for L G =70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.

In this paper, a realistic atomic model is used to study the atomic ordering effect on electronic structures of Si 0.5 Ge 0.5 . The hybrid density functional theory (DFT), HSE06, is chosen as the methodology. The calculated bandgap and effective masses of Si and Ge at various symmetry points are first validated by the reported experimental data and empirical pseudo-potential method (EPM) calculations. The study of two different Si 0.5 Ge 0.5 atomic configurations shows that the SiSi-GeGe case is more stable than SiGe-SiGe (RS2 structure). In addition, the electron effective masses of the former one are larger than those of the latter one, and those calculated by EPM with virtual crystal approximation (VCA). This large electron effective mass is attributed to the localized electron orbital of the lowest anti-bonding state in the SiSi-GeGe case which leads to a flat E-k curve. However, no obvious ordering effect on hole effective mass is found.

High-k/InAs interfaces have been manufactured using InAs surface oxygen termination and low temperature atomic layer deposition of HfO2. Capacitance–voltage (C–V) curves revert to essentially classical shape revealing mobile carrier response in accumulation and depletion, hole inversion is observed, and predicted minority carrier response frequency in the hundred kHz range is experimentally confirmed; reference samples using conventional techniques show a trap dominated capacitance response. C–V curves have been fitted using advanced models including nonparabolicity and Fermi-Dirac distribution. For an equivalent oxide thickness of 1.3 nm, an interface state density Dit = 2.2 × 1011 cm−2 eV−1 has been obtained throughout the InAs bandgap. The authors would like to thank Y. C. Sun of TSMC and L. Samuelson of Lund University for their support.

In this letter, a high-k composite oxide composed of La 2 O 3 and HfO 2 is investigated for n-In 0.53 Ga 0.47 As metal-oxide-semiconductor (MOS) capacitor application. The composite oxide was formed by depositing five layers of La 2 O 3 (0.8 nm)/HfO 2 (0.8 nm) on InGaAs with post deposition annealing at 500°C. The MOS capacitors fabricated show good inversion behavior, high capacitance, low leakage current, with excellent interface trap density (D it ) of 7.0×10 11 cm -2 eV -1 , small hysteresis of 200 mV and low capacitance equivalent thickness of 2.2 nm at 1 kHz were also achieved.