Logic

We demonstrated that the fundamental scaling challenges of carrier transport and device variability can be tackled by S/D epitaxy and HK/MG RPG optimizations on the leading-edge 7nm Si n FinFETs, paving the way for continuous scaling. Mitigations of S/D long-range Coulomb interactions and gate-corner work-function roll-up enhance IDSAT by 18% and 9% respectively at constant gate overdrive, translating to a 13% speed-power enhancement in the ring oscillator. These techniques show larger IDSAT enhancements than that of IDLIN. By using an improved characterization method, their unique transport characteristics are clarified.

The electrical characteristics of <110> n/p Ge nanowire transistors (NWTs) with the cross section of 6×6nm2 have been studied. The ION performance and the subthreshold swing are simulated by multi-subband Boltzmann transport equation and ballistic quantum transport solvers, respectively. The performance of <110> nGe NWTs is sensitive to the barrier height of interfacial layer due to highly-anisotropic Λ-valleys. The dimension-dependent k·p parameters based on tight-binding full band are used to address the strong confinement of pGe NWTs. Comparing to Si NWTs, the intrinsic ION is twice as high for both n/p Ge NWTs at 28nm channel length. As the channel length is scaled down, such ION benefit is maintained till the tunneling effect comes in and degrades the subthreshold swing.

The integration of III-V semiconductors on silicon (Si) substrate has been an active field of research for more than 30 years. Various approaches have been investigated, including growth of buffer layers to accommodate the lattice mismatch between the Si substrate and the III-V layer, Si- or Ge-on-insulator, epitaxial transfer methods, epitaxial lateral overgrowth, aspect-ratio-trapping techniques, and interfacial misfit array formation. However, manufacturing standards have not been met and significant levels of remaining defectivity, high cost, and complex integration schemes have hampered large scale commercial impact. Here we report on low cost, relaxed, atomically smooth, and surface undulation free lattice mismatched III-V epitaxial films grown in wide-fields of micrometer size on 300 mm Si(100) and (111) substrates. The crystallographic quality of the epitaxial film beyond a few atomic layers from the Si substrate is accomplished by formation of an interfacial misfit array. This development may enable future platforms of integrated low-power logic, power amplifiers, voltage controllers, and optoelectronics components.

In 0.53 Ga 0.47 As FinFETs are fabricated on 300 mm Si substrate. High device performance with good uniformity across the wafer are demonstrated (SS=78 mV/dec., I on /I off ~10 5 , DIBL=48 mV/V, g m =1510 μS/μm, and I on =301 μA/μm at V ds =0.5V with L g =120 nm device). The extrinsic field effect mobility of 1731 cm 2 /V-s with EOT~0.9nm is extracted by split-CV. Devices fabricated on 300mm Si have shown similar performances in SS and I on when benchmarked with device fabricated on lattice-matched InP substrate. In addition, an I on of 44.1 μA per fin is observed on the fin-height of 70 nm and the fin-width of 25nm, which is among the highest values reported for In 0.53 Ga 0.47 As FinFETs to the best of our knowledge.

InAs nanowires (NW) grown by MOCVD with diameter d as small as 10 nm and gate-all-around (GAA) MOSFETs with d = 12-15 nm are demonstrated. I on = 314 μA/μm, and S sat =68 mV/dec was achieved at V dd = 0.5 V (I off = 0.1 μA/μm). Highest g m measured is 2693 μS/μm. Device performance is enabled by small diameter and optimized high-k/InAs gate stack process. Device performance tradeoffs between g m , R on , and I min are discussed.

We report the first demonstration of InAs FinFETs with fin width W fin in the range 25-35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height H fin = 20 nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length L g = 1 μm, peak transconductance gm,peak = 1430 μS/μm is measured at V d = 0.5 V demonstrating that electron transport in InAs fins can match planar devices.

We report an in-depth atomistic study of the scaling potential of III-V GAA nanowire heterojunction TFET using an innovative tight-binding mode space (MS) technique with large speedup (up to 250×) while keeping good accuracy (error <; 1%). It is shown that both n- and pTFET performances are best above 20 nm gate length for a cross-section of 5.5 nm in the [111] crystal orientation. At V dd = 0.3 V and I off = 50 pA/μm, the on-current (Ion) and energy-delay product (ETP) gain over a Si NW GAA MOSFET are 58× and 56× respectively. In a beyond 5 nm node low power ITRS 2.0 horizontal GAA design rule however, where the gate length is restricted to 12 nm, a [100] orientation is best but features up to 3× I on and 2.4× ETP degradation vs. the 20 nm TFET GAA design.

We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration (VLSI)-compatible flow. Scaling of the equivalent oxide thickness EOT in conjunction with high-κ dielectric engineering improves the device performance; with an optimized gate stack having an EOT of 1.0 nm, the sub-threshold swing S is 76.8 mV/dec., and the peak transconductance gm is 1.65 mS/μm, at V ds of 0.5 V, for a gate-all-around nanowire MOSFET having a gate length L g of 90 nm, a nanowire height H NW of 25 nm, and a nanowire width W NW of 20 nm, resulting in Q ≡ gm/S = 21.5, a record for InAs on silicon. Furthermore, we report a source/drain resistance R sd of 160-200 Ω·μm, amongst the lowest values reported for III-V MOSFETs. Our VLSI-compatible process provides high device yield, which enables statistically reliable extraction of electron transport parameters, such as unidirectional thermal velocity vtx of 3-4×10 7 cm/s and back-scattering coefficient r c as a function of gate length.

This work investigates the formation mechanism of stress memorization technique (SMT)-induced edge dislocations and stacking faults during solid-phase epitaxy regrowth (SPER) using molecular dynamics (MD) simulation. During the SPER process of a patterned amorphous Si under a high-tensile capping film, growth fronts along the (1 1 0) and (0 0 1) planes collapse to form 5- and 7-rings which trigger the Frankel partial dislocation in the {1 1 1} plane. In addition, the line defects of stacking faults along {1 1 1} plane are generated with two symmetric boundaries of atomic structures which are confirmed as micro-twin defects. The MD simulation results are validated using high-resolution transmission electron microscopy and inverse fast Fourier transform images. The strain distribution obtained from the atomic structure reveals that the stress field is mainly caused by Frankel partial dislocations and the minor stress effect from the micro-twin defects.

This work highlights the impact of SMT-induced edge-dislocation positions in nFET device design. Based on experimental results and atomic transport simulation, dislocations with reduced proximity and depth would increase the amount of SFs and TDs which induce high parasitic resistance and high I boff leakage current together. Trade-off among strained mobility, parasitic resistance and I boff should be made for advanced device design.