Logic

Using a tight-binding mode-space NEGF technique, we explore the essential physics, design and performance potential of the III-V core-shell (CS) nanowire (NW) heterojunction tunneling field-effect transistor (TFET). The CS TFET “line-tunneling” current increases significantly with the core diameter d C and outperforms the best III-V axial “point-tunneling” NW heterojunction TFET I ON by up to 6× for d C = 6.6 nm. Reaching such a high level of current at low supply voltage, however, requires and involves specific and sometime unanticipated optimizations and physics that are thoroughly investigated here. In spite of the commonly accepted view, we also show and explain the weak gate-length dependency observed for the line-tunneling current in a III-V TFET. We further investigate the effect of electron-phonon scattering and discrete dopant impurity band tails on optimized CS NW TFETs. Including those non-idealities, the CS-TFET inverter performance significantly outperforms that of the axial TFETs. The low-power (LP) V DD = 0.35V CS-inverter delay is comparable to that of the high-performance (HP) Si CMOS using V DD = 0.55, which shows promise for an LP TFET technology with HP speed.

For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS 2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS 2 channels on SiO x /Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10 6 , a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).

Tunneling Field-Effect Transistors (TFET) are one of the most promising candidates for future low-power CMOS applications including mobile and Internet of Things (IoT) products. A vertical gate-all-around (VGAA) architecture with a core shell (C-S) structure is the leading contender to meet CMOS footprint requirements while simultaneously delivering high current drive for high performance specifications and subthreshold swing below the Boltzmann limit for low power operation. In this work, VGAA nanowire GaSb/InAs C-S TFETs are demonstrated experimentally for the first time with key device properties of subthreshold swing S = 40 mV/dec (Vd = 10 mV) and current drive up to 40 μA/wire (Vd = 0.3 V, diameter d = 50 nm) while dimensions including core diameter d, shell thickness and gate length are scaled towards CMOS requirements. The experimental data in conjunction with TCAD modeling reveal interface trap density requirements to reach industry standard off-current specifications.

Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS 2 p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS 2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS 2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of ~106, a S.S. of ~97 mV/dec., and nearly zero DIBL.

The increasing impact of self-heating effect (SHE) in complex FinFET structure is a serious reliability concern. Although the evaluation of SHE has become extremely arduous; this work proposes an in-situ layout based experimental solution to find out the precise thermal time constant (T TH ) due to SHE on advanced FinFET devices, even with the application of very pragmatic `circuit-like' gate and drain input waveforms. Using this precise T TH , the accurate dynamic thermal profile is found out from SPICE simulations. Finally, the true degradations due to different reliability mechanisms are evaluated including SHE impact and successfully compared with measured FinFET silicon data.

A new wafer-level coupling plasma charge recorder fabricated with 7nm FinFET CMOS logic process is presented in this paper. This plasma ion charge recording device provides the historic and quantitative plasma ion charges of damascene metallization steps in advanced 7nm FinFET COMS logic processes. The high-resolution plasma ion recorder is formed by an accurate FinFET coupling structure to store the plasma ion level and distribution of the whole wafer. By a simple wafer-level WAT measurement, the promising plasma charge recording device can efficiently collect the accumulated ion charges, ion polarization, and tiny plasma fluctuation of each metallization process step in 7nm FinFET CMOS logic technologies, which definitely provides a superior device and method in developing a reliable and non-latent plasma damage process for 7nm FinFET technology and beyond.

We present (i) a novel, thermally stable Atomic Layer Deposition (ALD) high-k dielectric stack that, for the first time, has the potential to meet all gate stack requirements for both n- and p-channel Ge FETs, (ii) record low contact resistivity for n-Ge/metal contacts using an implant-free contact scheme with successful implementation into a single nanowire (NW) Ge nFET baseline, (iii) single NW Ge pFETs with short-channel effect (SCE) immunity down to 24 nm physical gate length, of which electrical data show excellent agreement with calibrated models and (iv) demonstration of Ge-channel vertically stacked lateral NW FETs using a 300 mm VLSI compatible platform.

We demonstrated that the fundamental scaling challenges of carrier transport and device variability can be tackled by S/D epitaxy and HK/MG RPG optimizations on the leading-edge 7nm Si n FinFETs, paving the way for continuous scaling. Mitigations of S/D long-range Coulomb interactions and gate-corner work-function roll-up enhance IDSAT by 18% and 9% respectively at constant gate overdrive, translating to a 13% speed-power enhancement in the ring oscillator. These techniques show larger IDSAT enhancements than that of IDLIN. By using an improved characterization method, their unique transport characteristics are clarified.

The electrical characteristics of <110> n/p Ge nanowire transistors (NWTs) with the cross section of 6×6nm2 have been studied. The ION performance and the subthreshold swing are simulated by multi-subband Boltzmann transport equation and ballistic quantum transport solvers, respectively. The performance of <110> nGe NWTs is sensitive to the barrier height of interfacial layer due to highly-anisotropic Λ-valleys. The dimension-dependent k·p parameters based on tight-binding full band are used to address the strong confinement of pGe NWTs. Comparing to Si NWTs, the intrinsic ION is twice as high for both n/p Ge NWTs at 28nm channel length. As the channel length is scaled down, such ION benefit is maintained till the tunneling effect comes in and degrades the subthreshold swing.