Logic

We demonstrate, for the first time, an integration-friendly selective PMOSFET fully silicided (FUSI) gate process. In this process, a millisecond-anneal (MSA) technique is utilized for the nickel silicide phase transformation. A highly tensile FUSI gate electrode is created and hence exerts compressive stress in the underlying channel. The highly flexible integration scheme successfully, and exclusively, implements uniform P + FUSI gates for PMOSFETs while preserving a FUSI-free N + poly-Si gate for NMOSFETs with the feature size down to 30 nm. A 20% improvement in FUSI- gated PMOSFET I on - I off is measured, which can be attributed to the enhanced hole mobility and the elimination of P + poly-gate depletion.

A 32 nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 muA/mum (n/p) are achieved at I off =100 nA/mum, V dd =1 V, 30 nm physical gate length and 130 nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of 1020/700 muA/mum (n/p) at total I off ~1 nA/mum @ V dd = 1V. Low sub-threshold leakage was achieved while successfully containing I boff and I goff well below 1 nA/um. Ultra high density 0.15 um 2 SRAM cell is fabricated by high NA 193 nm immersion lithography. Functional 2 Mb SRAM test-chip in 32 nm design rule has been demonstrated with a controllable manufacturing window.

A continuum model of phosphorus diffusion with germanium and carbon coimplant has been proposed and calibrated based on secondary ion mass spectroscopy (SIMS) profiles aiming at ultra shallow junction (USJ) formation in advanced CMOS technologies. The phosphorus diffusion behaviors are well captured by our model under various implant and annealing conditions, representing a significant step towards advanced n-type USJ formation technique using phosphorus and carbon coimplant for aggressively scaled CMOS technologies.

Highest planar HK/MG PFET performance (I ON = 790 muA at I off = 100 nA, Vdd= 1 V and Lg= 33 nm) has been demonstrated with a gate-first dual-metal CMOS integrated process and proven by functional SRAM cell. Integrating modern stressors without IL re-growth and achieving band edge work function without increasing T INV are two major challenges for gate-first HK/MG processes. In this work, band-edge effective work function has been achieved without increasing T INV . Furthermore, with successful integration of stress techniques like SiGe-S/D, SMT and CESL, not only performance was improved by 30% but also no reliability degradation was observed. Finally, no degradation from decreasing poly-pitch also suggests its good scalability to next generations.

For the first time, we present a state-of-the-art 32 nm low power foundry technology integrated with 0.15um 2 6-T high density SRAM, low standby transistors, analog/RF functions and Cu/low-k interconnect for mobile SoC applications. To our knowledge, this is the smallest fully functional 2Mb SRAM test-chip for 32nm node. Low power transistors with Lg of 30nm achieve current drive of 700/380 uA/um at 1.1V and off-leakage current of 1 nA/um for NMOS and PMOS, respectively. An NPoly/NWell MOS varactor shows capacitance ratio of >5.0. The MOM unit capacitance of 3.5 fF/um 2 is achieved with only 4 metal layers.

A highly scaled, high performance 45 nm CMOS technology utilizing extensive immersion lithography to achieve the industry's highest scaling factor with ELK (k=2.55) BEOL is presented. A record gate density 2.4X higher than that of 65 nm is achieved. Refined strained-CMOS demonstrated 1200/750 μA/μm Idsat at 100 nA/μm Ioff, Vdd=1 V, which has the best Ion-Lg performance reported for bulk CMOS device. The proposed 45 nm technology is not only manufacturing friendly but also has well-controlled leakage and mismatch evidenced by a functional 32 Mb 0.242 μm 2 SRAM.

In this paper, we present an advanced integration approach using milli-second anneal technique to enhance device performance. In addition to enhanced poly-silicon activation, the device gain resulted from channel stress modulation, and retarded dopant diffusion can be obtained through process optimization including rapid-thermal anneal (RTA), capping layer, and milli-second anneal. More than 15% NMOS performance gain is demonstrated without undergoing milli-second-anneal-induced pattern loading effect and re-crystallization defect. No obvious stress relaxation and driving current degradation are observed in epi-SiGe PMOS. Moreover, the performance gain is increased while lowering the RTA temperature, suggesting that our proposed approach may open an alternative pathway for 45nm technology node and beyond

Mobility enhancement techniques have become pervasive in advanced CMOS technologies. Non-scalable and scalable approaches to mobility enhancement are widely used in various application segments (high-speed, low-operating power, and low- standby power). Non-scalable techniques rely on preferential channel directions having fundamentally higher carrier mobility than the conventional <110> directions of (100) substrates. On the other hand, scalable techniques rely on process built-in mechanical strain to boost mobility as a result of band- structure response impacting both carrier-effective mass and scattering rates. Scalable techniques are based on the channel strain induced by contact-etch stop layers or Si(1-x)Ge(x) structures primarily. This paper will review both non-scalable and scalable mobility enhancement approaches from two angles, namely fundamental device physics and overall device integration schemes. The paper will also review and discuss issues related to superposition of process built-in strain for performance enhancement.

In this work, a simplified BSIM-based model has been proposed to solve the above issues contributed by halo implants [Goto, K, et al., 2003]. In this new methodology, R sd and mu eff can be uniquely extracted in nano-scale devices. Furthermore, the extracted L G dependency of mu eff may serve as a good indicator for monitoring the relationship between geometry and stress parameters

A 1.4 nm EOT stack film of HfSiON with interfacial oxide layer (IL) is demonstrated with excellent electrical characteristics and reliability for 45 nm node low-power technology. Mobility comparable to SiON is achieved along with adequate nMOS PBTI lifetime, TDDB lifetime, and breakdown voltage (V BD ). For the first time, we report lower V BD for the HfSiON stack film despite of 3 orders gate leakage reduction compared to the same EOT SiON. It is attributed to IL breakdown in the proposed two-step breakdown mechanism. This possibly limits the scalability of such a stack film. On the other side, over-drivability of HfSiON with thick underlying oxide boosts input/output (I/O) device performance significantly