High-Performance Integrated Fan-Out Wafer Level Packaging (InFO-WLP): Technology and System IntegrationIntegrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLP's high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.
A novel LWR reduction approach to enhance reliability performance in ultra-thin barrier/porous low-k (K<2.4) interconnectThis study evaluated plasma treatment processes on 193i and EUV photoresist to improve the line width roughness (LWR) performance in porous low-k/ultra-thin barrier Cu interconnect. We successfully demonstrated 20% LWR reduction for 193i PR and 11% for EUV PR. Furthermore, the influence of LWR on reliability was evaluated on 45nm line-width test vehicle. A boost of 10 times Time Dependent Dielectric Breakdown (TDDB) and 2 times Eelectrical Migration (EM) was demonstrated.
Uncured ELK as a chemical mechanical planarization stop layer in Cu/XLK interconnectA novel approach of copper CMP stop layer using uncured extreme low-K was demonstrated to improve the within-wafer Rs uniformity on Cu/extra low-k (XLK) interconnect. This CMP stop layer could be converted into a low dielectric constant film by removing porogen with post CMP treatment, hence its impact on overall’s film capacitance is minimized.
An ultra-thin interposer utilizing 3D TSV technologyTo achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200 μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer.
Advanced Reliability Study of TSV Interposers and Interconnects for the 28nm Technology FPGATSV interposer has emerged as a good solution to provide high wiring density interconnections, improved electrical performance due to shorter interconnection from the die to substrate, and minimized CTE mismatch between the chip and copper filled TSV interposer, resulting in high reliability micro bumps and more reliable low-k chip. Furthermore, for an interposer that does not contain any active device, already established process technology could be applied, TSV pitch could be coarser and a thicker interposer could be used. This paper presents the development of TSV interposer technology for a high-performance 28nm logic die that is mounted on a large silicon interposer with Cu through silicon via. A representative silicon interposer test chip with thousands of micro-bumps at 45um pitch has been fabricated. The silicon interposer is 100um thick, and is mounted on a 42.5mm×42.5mm substrate through 180um pitch C4 bumps. TSV fabrication process steps and assembly process of the large logic die mounted on the TSV interposer with lead-free micro-bumps have been optimized as well as assembly of the component on the organic substrate. 3D thermal-mechanical modeling and simulation for the packaged device with TSV interposer have been performed. The samples have been subjected to thermal cycling, electro-migration and moisture sensitivity tests. Effect of TSV interposer on the stress of the die, low-k layers and fatigue life of micro bumps and C4 bumps have been investigated. Several DOEs have been performed to optimize design and material selection in order to maximize yield and reliability. Finally, Si interposer seemed to be a low-risk 3D path to have a reliable package with acceptable warpage/coplanarity, passing 1000TCB without any crack, delamination or void being detected in low-k, TSV, micro bumps and C4 bumps.
Low damage etch approach for next generation Cu interconnectThis research focus on low radical plasma etch (LRPE) process and its impact on highly porous dielectric material (extreme-low-k, ELK, k=2.4). We demonstrate a dual damascene (DD) process flow without k degration by low radical and pore sealing plasma etch. Comparing to tranditional DD etching process, 12% resistance-capacitance (RC) improvement, 15% via resistance reduction and a factor of 3 inter-metal-dielectric (IMD) time dependent dielectic breakdown (TDDB) improvement can be achieved by the proposed approach.
A new enhancement layer to improve copper interconnect performanceThis study reports the effect of different barrier on Cu interconnect performance. A thin “enhancement” layer of Ru or Co film is deposited between a PVD Ta(N) liner barrier and a Cu seed layer to improve copper to barrier adhesion and copper gap fill. With the enhancement layer of either Ru or Co, no void is found in dual damascene structure with very thin seed. The electrical performance is improved with more than two times of EM lifetime is observed. The seedless electroplating on the enhancement layers capability will maximize the gap fill window.
Challenges of Low Effective-K approaches for future Cu interconnectChallenges of various low effective-K approaches, including homogeneous low-K and air-gap, for next generation Cu/low-K interconnect will be presented. For homogeneous low-K approach, top issues and possible solutions for K damage, package, and CMP peeling & planarization due to introduction of fragile lower k (KLt2.4) insulator will be focused. For air-gap, various types of air-gaps will be reviewed from the points of cost, layout/designer, and new processes involved.
Low capacitance approaches for 22nm generation Cu interconnectVarious integration approaches, including homogeneous porous Low-k and air gaps, for low-capacitance solution were investigated for 22 nm Cu interconnect technology and beyond. For homogeneous Low-k approach, K=2.0 Low-k material is successfully integrated with Cu. Up to 15% line to line capacitance reduction compared with LK-1 (K= 2.5) was demonstrated by a damage-less etching and CMP process. For air gap approach, a cost-effective and Selective air gaps formation process was developed. Air gaps are selectively formed only at narrow spacing between conduction lines without additional processes.
Diffusion of Copper in Titanium Zirconium Nitride Thin FilmsThe diffusion coefficient of Cu in (Ti, Zr)N was measured by X-ray diffraction (XRD) and four-point probe (FPP) analyses after annealing Cu/(Ti, Zr)N/Si multilayered samples in the temperature range of Cu diffusion in (Ti, Zr)N had components from both the grain boundaries and the lattice based on diffusional analysis. This study suggests that for the measurement of the diffusion coefficient of Cu, FPP analysis is more precise and sensitive than XRD analysis. Additionally, (Ti, Zr)N has better Cu diffusion barrier properties than those of TaN and TiN. © 2004 The Electrochemical Society. All rights reserved.
Interconnect is critically important for system performance. They are structures that connect two or more circuit elements (such as transistors) together electrically. In the past, interconnect was often referred to as on-chip interconnect of integrated circuits. Nowadays interconnect generally includes both on-chip interconnect of integrated circuits and off-chip interconnect in heterogeneous system integration. In interconnect design, geometric dimensions (width, thickness, spacing, aspect ratio, pitch), materials, process control and design layout are all critical to proper interconnect function, performance, power efficiency, reliability, and fabrication yield.