Interconnect

The RC delay, electro migration (EM) and TDDB performance become more challenges to meet device requirement as continuous geometry shrink on BEOL dual damascene interconnects. To overcome these challenges from interconnect patterning point of view, we proposed Cu subtractive RIE as a potential solution for next generation Cu/Low-k interconnects.

As dimension shrinks the volume percent occupied by conventional barrier and liner increases and line resistance (Rs) and via resistance (Rc) increases dramatically. An ultrathin ALD MnN barrier is being evaluated as a single layer barrier for resistance reduction in small structures. >20% and >80% Rs and Rc reduction was demonstrated, while 4× better mean time to failure (MTTF) on the time dependent dielectric breakdown (TDDB) was achieved comparing to conventional barrier/liner. ALD MnN is a potential barrier candidate for future interconnects technology.

Advanced mobile computing devices nowadays demand for ever-increasing functionality, performance and bandwidth. The complexity of functional integration in mobile device has made it more challenging for wire bond and C4 bump flip chip packaging to meet the requirement of high I/O count and high density integration. Moreover, the extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) must be utilized to meet performance requirements from the advanced silicon technology nodes. In this paper, the maximum ELK stress for advanced mobile SoC integrated by different packaging technologies, aka integrated fan-out (InFO), chip last fan-out wafer level package (CL-FOWLP), and flip chip package, were evaluated by FEA first. Then the governing mechanisms behind the ELK stress were analyzed. The InFO outperforms CL-FOWLP and flip chip package in the maximum ELK stress due to its simplified architecture and fabrication process. With a low ELK stress, InFO technology can play an important role in enabling more advanced mobile ICs and high performance SoC packaging for the future 4C applications.

Steady-state and transient thermal performance of a novel memory-integrated 3D-stacking packaging technology, integrated fan-out package-on-package (InFO_PoP), developed for state-of-the-art mobile applications were experimentally characterized using a specially designed thermal test vehicle. Two competing technologies, flip-chip PoP (FC_PoP) and 3DIC, are also included in this study as the reference for thermal performance benchmark. Direct thermal performance comparison is made possible by the data collected on the comparable FC_PoP thermal test vehicles. Thermal models have been successfully developed to enable further study on the cross-package performance comparison, as well as the impact of various key package design parameters. With the innovative approach replacing the organic substrate with thermally favorable RDL layers, a typical InFO_PoP package has 12% and 17% lower junction-to-ambient thermal resistance than a typical FC_PoP and 3DIC package, respectively. The appealing transient thermal response also makes the InFO_PoP the most competitive 3D packaging technology in high-performance mobile applications. Although the strong thermal interactions between the component packages of a PoP package complicates the thermal analysis, power envelop is proposed and demonstrated as a useful tool for package thermal design optimization. In addition, transient thermal analysis is recommended as a supplementary thermal design approach to the commonly used steady-state thermal analysis.

A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices. This novel InFO technology is the first high performance Fan-Out Wafer Level Package (FO_WLP) with multi-layer high density interconnects proposed to the industry. In this paper we present the detailed comparison of InFO packages on package (InFO_PoP) with several other previously proposed 3D package solutions. Result shows that InFO_PoP has more optimized overall results on system performance, leakage power and area (form factor) than others, to meet the ever-increasing system requirements of mobile computing. InFO technology has been successfully qualified on package level with robust component and board level reliability. It is also qualified at interconnect level with high electromigration resistance. With its high flexibility and strong capability of multi-chips integration for both homogeneous and heterogeneous sub-systems, InFO technology not only provides a system scaling solution but also complements the chip scaling and helps to sustain the Moore's Law for the smart mobile as well as internet of things (IoT) applications.

A novel integrated fan-out package on package (InFO_PoP) technology for application processor (AP), memory, and PMIC system is developed for next generation high performance mobile applications. For AP and memory system, the InFO_PoP technology can provide better system performance and lower package profile, compared to current flip-chip package on package (FC_PoP) technology. For signal integrity, the eye height of eye diagram for the InFO_PoP is 24% larger than that for the FC_PoP at LPDDR4. For power integrity, the PDN impedance for the InFO_PoP is 84% lower than that for the FC_PoP at high frequency because of thinner dielectric layer between power/ground planes and shorter path from AP pad to PCB. For AP and PMIC system, an advanced power delivery network (PDN) is proposed to minimize the supply voltage variation and transient time using face-to-face interconnection between AP package and partitioned voltage regulators (PVRs) chip from PMIC package. The voltage variation of the InFO_PoP with PVRs system is 43% lower than that of the FC_PoP with PVRs system. Meanwhile, the InFO_PoP with PVRs system exhibits immediate transient response. The transient time of InFO_PoP with PVRs system is 54% less than that of the FC_PoP with PVRs system.

A novel 3D InFO inductor is developed to integrate with TSMC 16nm FinFET devices for high efficiency integrated voltage regulator (IVR) design. The 3D InFO inductor is designed using thick through-InFO-via (TIV) copper, where the form factor is 1.4 × 2.2 × 0.15 mm 3 . It performs 2.14 nH inductance at 140 MHz and 3.2 mΩ resistance at DC. The resistance of power delivery network (PDN) between inductor and load is 1.1 mu. The InFO technology provides the low resistance 3D inductor and PDN concurrently for the IVR system design to achieve a peak power efficiency of 93%.

In this work, a low-resistance and low-cost PVD-TiZrN barrier is evaluated for BEOL interconnect. Comparing to conventional PVD barrier, comparable Cu barrier and Cu wetting properties are obtained. Moreover, up to 55% of via resistance reduction is achieved, with comparable voltage breakdown performance comparing to conventional one.

High performance passive devices for millimeter wave (MMW) system, including inductor, ring resonator, power combiner, coupler, balun, transmission line, and antenna, are first realized using integrated fan-out (InFO) wafer level packaging technology. The inductors has quality factor over 40; the power combiner, coupler, and balun show lower transmission loss than on-chip passives; antenna has the efficiency of over 60%. These devices on InFO enable low noise and power MMW system for mobile communication and IoT applications.

High stresses generated from chip-package interactions (CPI), especially when large die is flip mounted on organic substrate using Pb-free C4 bumps, can easily cause low-k delamination. A novel scheme by applying an elastic material can effectively reduce the transmitted stresses and, thus, resolve the interfacial delamination issue. Along with an optimized chip-package integration solution, a reliable interconnect structure with good electrical performance, has been successfully demonstrated.