Interconnect

Interconnect

Interconnect is critically important for system performance. They are structures that connect two or more circuit elements (such as transistors) together electrically. In the past, interconnect was often referred to as on-chip interconnect of integrated circuits. Nowadays interconnect generally includes both on-chip interconnect of integrated circuits and off-chip interconnect in heterogeneous system integration. In interconnect design, geometric dimensions (width, thickness, spacing, aspect ratio, pitch), materials, process control and design layout are all critical to proper interconnect function, performance, power efficiency, reliability, and fabrication yield.

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  • Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile Applications

    2016
    Steady-state and transient thermal performance of a novel memory-integrated 3D-stacking packaging technology, integrated fan-out package-on-package (InFO_PoP), developed for state-of-the-art mobile applications were experimentally characterized using a specially designed thermal test vehicle. Two competing technologies, flip-chip PoP (FC_PoP) and 3DIC, are also included in this study as the reference for thermal performance benchmark. Direct thermal performance comparison is made possible by the data collected on the comparable FC_PoP thermal test vehicles. Thermal models have been successfully developed to enable further study on the cross-package performance comparison, as well as the impact of various key package design parameters. With the innovative approach replacing the organic substrate with thermally favorable RDL layers, a typical InFO_PoP package has 12% and 17% lower junction-to-ambient thermal resistance than a typical FC_PoP and 3DIC package, respectively. The appealing transient thermal response also makes the InFO_PoP the most competitive 3D packaging technology in high-performance mobile applications. Although the strong thermal interactions between the component packages of a PoP package complicates the thermal analysis, power envelop is proposed and demonstrated as a useful tool for package thermal design optimization. In addition, transient thermal analysis is recommended as a supplementary thermal design approach to the commonly used steady-state thermal analysis.
  • InFO (Wafer Level Integrated Fan-Out) Technology

    2016
    A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices. This novel InFO technology is the first high performance Fan-Out Wafer Level Package (FO_WLP) with multi-layer high density interconnects proposed to the industry. In this paper we present the detailed comparison of InFO packages on package (InFO_PoP) with several other previously proposed 3D package solutions. Result shows that InFO_PoP has more optimized overall results on system performance, leakage power and area (form factor) than others, to meet the ever-increasing system requirements of mobile computing. InFO technology has been successfully qualified on package level with robust component and board level reliability. It is also qualified at interconnect level with high electromigration resistance. With its high flexibility and strong capability of multi-chips integration for both homogeneous and heterogeneous sub-systems, InFO technology not only provides a system scaling solution but also complements the chip scaling and helps to sustain the Moore's Law for the smart mobile as well as internet of things (IoT) applications.
  • Signal and Power Integrity Analysis on Integrated Fan-Out PoP (InFO_PoP) Technology for Next Generation Mobile Applications

    2016
    A novel integrated fan-out package on package (InFO_PoP) technology for application processor (AP), memory, and PMIC system is developed for next generation high performance mobile applications. For AP and memory system, the InFO_PoP technology can provide better system performance and lower package profile, compared to current flip-chip package on package (FC_PoP) technology. For signal integrity, the eye height of eye diagram for the InFO_PoP is 24% larger than that for the FC_PoP at LPDDR4. For power integrity, the PDN impedance for the InFO_PoP is 84% lower than that for the FC_PoP at high frequency because of thinner dielectric layer between power/ground planes and shorter path from AP pad to PCB. For AP and PMIC system, an advanced power delivery network (PDN) is proposed to minimize the supply voltage variation and transient time using face-to-face interconnection between AP package and partitioned voltage regulators (PVRs) chip from PMIC package. The voltage variation of the InFO_PoP with PVRs system is 43% lower than that of the FC_PoP with PVRs system. Meanwhile, the InFO_PoP with PVRs system exhibits immediate transient response. The transient time of InFO_PoP with PVRs system is 54% less than that of the FC_PoP with PVRs system.
  • Ultra-low-resistance 3D InFO inductors for integrated voltage regulator applications

    2016
    A novel 3D InFO inductor is developed to integrate with TSMC 16nm FinFET devices for high efficiency integrated voltage regulator (IVR) design. The 3D InFO inductor is designed using thick through-InFO-via (TIV) copper, where the form factor is 1.4 × 2.2 × 0.15 mm 3 . It performs 2.14 nH inductance at 140 MHz and 3.2 mΩ resistance at DC. The resistance of power delivery network (PDN) between inductor and load is 1.1 mu. The InFO technology provides the low resistance 3D inductor and PDN concurrently for the IVR system design to achieve a peak power efficiency of 93%.
  • Low-via-resistance and low-cost PVD-TiZrN barrier for Cu/low-K interconnects

    2016
    In this work, a low-resistance and low-cost PVD-TiZrN barrier is evaluated for BEOL interconnect. Comparing to conventional PVD barrier, comparable Cu barrier and Cu wetting properties are obtained. Moreover, up to 55% of via resistance reduction is achieved, with comparable voltage breakdown performance comparing to conventional one.
  • High performance passive devices for millimeter wave system integration on integrated fan-out (InFO) wafer level packaging technology

    2015
    High performance passive devices for millimeter wave (MMW) system, including inductor, ring resonator, power combiner, coupler, balun, transmission line, and antenna, are first realized using integrated fan-out (InFO) wafer level packaging technology. The inductors has quality factor over 40; the power combiner, coupler, and balun show lower transmission loss than on-chip passives; antenna has the efficiency of over 60%. These devices on InFO enable low noise and power MMW system for mobile communication and IoT applications.
  • A flexible top metal structure to improve ultra low-k reliability

    2015
    High stresses generated from chip-package interactions (CPI), especially when large die is flip mounted on organic substrate using Pb-free C4 bumps, can easily cause low-k delamination. A novel scheme by applying an elastic material can effectively reduce the transmitted stresses and, thus, resolve the interfacial delamination issue. Along with an optimized chip-package integration solution, a reliable interconnect structure with good electrical performance, has been successfully demonstrated.
  • Power Saving and Noise Reduction of 28nm CMOS RF SystemIntegration Using Integrated Fan-Out Wafer Level Packaging (InFO-WLP) Technology

    2015
    An integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of -53 dB. With the 3DSI, the RF system in the InFO technology results in power saving by 58% and noise reduction by 80% in LNA and VCO, respectively, compared with those in RF SoC system. The InFO technology provides a novel solution for RF system integration.
  • New System-in-Package (SiP) Integration technologies

    2014
    New System-in-Package (SiP) with innovative Wafer-Level-System-Integration (WLSI) technologies that leverage foundry core competence on wafer processes have been demonstrated. The WLSI technologies include Chipon-Wafer-on-Substrate (CoWoSTM) 3DIC and interposer, Integrated Fan-Out (InFO) and Chip-Scale Wafer-LevelPackaging. Wide application portfolio from very low I/O pin-count, low-cost devices, to medium, high and ultra-high pin-count are realized. Chip-partition followed by flexible powerful integration of single-chip or multi-chips, advanced or matured Si, logic and memory, SoC and sensor/MEMS. System values include low profile, low power, high bandwidth along with competitive cost can be readily achieved. With the chip-partition, we can sustain Moore’s law longer.
  • A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration

    2014
    A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (V cc ) of 1.8V, and a leakage current (I LK ) below 1 fA/μm 2 under +/-2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/μm 2 , respectively, with their corresponding I LK below 0.48, 0.19 and 0.09 fAmp/μm 2 . Process reliability related defect density (D 0 ) of the interposer HK-MiM is as low as 0.095% cm -2 as judged by a 10 years lifetime breakdown voltage (V bd ) criterion at V cc =3.2V. This low D 0 ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm 2 within the Si interposer. Moreover, the V bd tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., I LK & V bd tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.
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