Interconnect

Interconnect

Interconnect is critically important for system performance. They are structures that connect two or more circuit elements (such as transistors) together electrically. In the past, interconnect was often referred to as on-chip interconnect of integrated circuits. Nowadays interconnect generally includes both on-chip interconnect of integrated circuits and off-chip interconnect in heterogeneous system integration. In interconnect design, geometric dimensions (width, thickness, spacing, aspect ratio, pitch), materials, process control and design layout are all critical to proper interconnect function, performance, power efficiency, reliability, and fabrication yield.

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  • Wafer Level System Integration for SiP

    2014
    A family of novel wafer-level-system-integration technologies (WLSI) was proposed. This paper reviews WLSI feasibility work first. Further results on the reliability, the compatibility of the integration with both more advanced node Logic and DRAM devices, and the higher-level system integration of the WLSI technologies are then presented. Foundry has established a comprehensive system integration technology portfolio in wafer form to fulfill the needs from mobile to cloud computing for the future growth of the Si-based nano-electronics industry.
  • Reliability Evaluation of a CoWoS-enabled 3D IC Package

    2013
    TSV (Through Silicon Via)-based interposer has been proposed as a multi-die package solution to meet the rapidly increasing demand in inter-component (e.g. CPU, GPU and DRAM) communication bandwidth in an electronic system. he stacked-silicon die package configuration may give rise to package reliability concerns not observed in conventional monolithic flip-chip packages. 3D finite element method (FEM) was used to study the thermo-mechanical response of the interposer-based package during thermal cycle reliability stressing. Fatigue failures of the C4 and BGA joints are the two primary reliability focuses in the present study. Experimental data collected on the CoWoSTM-enabled test vehicles were used to validate the FEM models. Parametric study of key package material and geometric parameters was performed to analyze their effects on C4 bump thermal cycle reliability. Package materials of interest include UF (underfill), lid and substrate, and the geometric parameters include lid thickness and C4 bump scheme. The results showed that the CoWoS package using AlSiC lid has better C4 bump life than the CoWoS package using Cu lid, and when the Tg of the underfill of C4 bump is higher, the C4 bump has better reliability. Furthermore, 3D thermomechanical and reliability study of BGA balls is presented for organic and ceramic substrates. Several DOEs have been constructed for ceramic substrate to increase BGA reliability by optimizing C4 underfill material and package design. The effect of board layer count and design is detailed. Finally reliability of BGA balls, C4 and micro-bumps are compared for a part that is mounted on a PCB board.
  • Array Antenna Integrated Fan-out Wafer Level Packaging (InFO-WLP) for Millimeter Wave System Applications

    2013
    Array antenna integrated with RF chip using InFO-WLP technology is proposed for millimeter wave system applications. Aperture-coupled patch antenna is designed on the fan-out molding compound (MC). The performance of single-element antenna is evaluated first and proved to have 5 dBi of gain. Meanwhile, the interconnect from chip to antenna feeding line is demonstrated to only have 0.7 dB loss, which can save 19 % PA output power compared with that of flip-chip package. Finally, the system performance of 4 × 4 antenna array integrated with RF chip on the InFO structure shows 14.7 dBi of array gain in a small form factor of 10 × 10 × 0.5 mm 3 .
  • Innovative Wafer-based Interconnect Enabling System Integration and Semiconductor Paradigm Shifts

    2013
    In semiconductor world, there is a new paradigm shift from chip-scaling to system-scaling to meet the ever-increasing electronic system demands for performance and functionality, and for reduction of system form factor, power and cost. This shift is also triggered by the fast increasing challenges for industry to sustain Moore's Law. System scaling needs advanced package technologies. Conventionally, package technologies use different tool sets and different materials from those used in wafer fab. Innovative wafer-based technology is proposed here to fabricate advanced packaging that, in turn, enables the system scaling - a new paradigm shift. Another new paradigm shift enabled here is that the advanced packaging shifts from conventional packaging to the innovative wafer-based technology. The innovations cover three major system scaling architecture/technologies: wafer-level-packaging (fan-in and fan-out), through-Si-via (3DIC and interposer) and ultra-thin package-on-package (PoP) for both high performance and mobile devices. We also re-invent microelectronics, continue delivering more advanced electronic systems, and help to sustain Moore's Law.
  • High-Performance Inductors for Integrated Fan-Out Wafer Level Packaging (InFO-WLP)

    2013
    Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art quality factor (Q) = 64 in 2.4GHz inductor has been demonstrated for RF systems. For the first time, radio frequency (RF) circuits with InFO-WLP have been fabricated to illustrate how the high Q inductor can be used to dramatically improve performance and power consumption concurrently.
  • Manufacturability Optimization and Design Validation Studies for FPGA-Based, 3D Integrated Circuits

    2013
    Heterogeneous integration of integrated circuits offers an opportunity to create new functionality with tradeoffs between cost, performance, and alternative monolithic integration complexity. We present a study of heterogeneous integration using a large, field programmable gate array (FPGA) research and development vehicle to assess the capabilities of 3D silicon interposer technology. This study includes integration on a silicon interposer of a monolithic high-performance FPGA product with a companion test chip, manufacturing flow optimization for yield and reliability, design optimization, and characterization studies. High yield and reliability metrics were achieved through stress management, robust design, and manufacturing flow optimizations. Characterization results show minimal performance impact due to through silicon via (TSV) to 10Gbps transceivers and potential improvement in performance by integrating metal-insulator-metal (MIM) capacitor on the silicon interposer. Co-design implications for 3D product integration of large, high performance FPGA's with companion die will be discussed.
  • High-Performance Integrated Fan-Out Wafer Level Packaging (InFO-WLP): Technology and System Integration

    2012
    Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLP's high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.
  • A novel LWR reduction approach to enhance reliability performance in ultra-thin barrier/porous low-k (K<2.4) interconnect

    2012
    This study evaluated plasma treatment processes on 193i and EUV photoresist to improve the line width roughness (LWR) performance in porous low-k/ultra-thin barrier Cu interconnect. We successfully demonstrated 20% LWR reduction for 193i PR and 11% for EUV PR. Furthermore, the influence of LWR on reliability was evaluated on 45nm line-width test vehicle. A boost of 10 times Time Dependent Dielectric Breakdown (TDDB) and 2 times Eelectrical Migration (EM) was demonstrated.
  • Uncured ELK as a chemical mechanical planarization stop layer in Cu/XLK interconnect

    2012
    A novel approach of copper CMP stop layer using uncured extreme low-K was demonstrated to improve the within-wafer Rs uniformity on Cu/extra low-k (XLK) interconnect. This CMP stop layer could be converted into a low dielectric constant film by removing porogen with post CMP treatment, hence its impact on overall’s film capacitance is minimized.
  • An ultra-thin interposer utilizing 3D TSV technology

    2012
    To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200 μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer.
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