Superpolishing for Planarizing Copper Damascene InterconnectsWe demonstrate a superpolishing electrolyte, which consists of acid additives in conventional Cu polishing electrolytes for efficiently planarizing Cu damascene features. The significant additive concentration gradient in features, resulting in a selective Cu dissolution rate within features, is explored as a major mechanism that yields such electrolytes with high planarization efficiency. Moreover, another additive, polyethylene glycol as a suppressor, is also employed to reduce oxygen bubbling on polished films. Consequently, a smooth surface with a complete step height elimination is obtained in a 70 μm trench after electropolishing.
High performance/reliability Cu interconnect with selective CoWP capIn this work, a selective CoWP metal cap was employed after Cu CMP process for replacing conventional dielectric cap layer platform. A 5% reduction in RC delay was demonstrated for this new approach. The CoWP cap layer improves the interface between Cu and dielectric layer which reduces the Cu surface migration. EM for both via and trench shows more than 10X improvement. With optimized thickness and deposited process, 100% yield of line to line leakages, via chain Rc, and metal line Rs can be achieved. A semi-quantitative model was employed to determine surface migration dominating EM failure.
90 nm generation Cu/CVD low-k (k < 2.5) interconnect technologyEight level Cu/CVD low-k (k<2.5) + one top level Cu/USG 90 nm multilevel interconnection with 0.12/0.12 /spl mu/m for line width/space and 0.13 /spl mu/m for via has been demonstrated for the first time using 193 nm lithography with OPC developed for TSMC 200 mm/300 mm technologies. The 8-level Cu/CVD low-k dual damascenes were constructed by nitrogen-free dielectric layers without middle trench etch stop to achieve keff=2.6. No film delamination was found by film and CMP optimization. Electrical results showed that excellent and thermally stable metal-line Rs and via-chain Rc yields from iso or dense Cu areas and 1M via chains were obtained.
A 90 nm generation copper dual damascene technology with ALD TaN barrierAs the device dimension continues to shrink, the need for a thinner barrier for copper has risen in order to meet the requirements for future device performance. The conventional barrier process by physical vapor deposition (PVD) has the limitation to achieve conformal step coverage across the dual damascene structure , and therefore would face a bottleneck when the thickness reduction is required. In this work, the atomic layer deposition (ALD) technique is applied for the TaN barrier process of a 90 nm generation copper dual damascene integration with low-k dielectrics of k=3.0. The ALD technique could not only provide a conformal step coverage on both trenches and vias, it could also allows reasonable thickness control for thickness of the order of 10 /spl Aring/. The integration results show that ALD TaN has promising electrical performance on sheet resistance, via resistance, and line-to-line leakage, and it also has superior reliability performance on electromigration, stress migration, and bias temperature test as compared with conventional PVD TaN.
CVD barriers for Cu with nanoporous ultra low-k: integration and reliabilityThe drive for greater integrated circuit performance has led to the need for faster interconnect systems, the development of porous ultra low-k dielectrics and thin CVD barriers. The porous structure and lower modulus of low-k dielectrics has made integration a greater challenge. In this paper, we report on an initial feasibility study on of a new spin-on nanoporous low-k dielectric with a CVD TiN(Si) barrier, for Cu dual damascene integration.
CMP-free and CMP-less approaches for multilevel Cu/low-k BEOL integrationA CMP-free process by electropolishing (EP) the planar contact plating (CP) Cu film and TaN dry etching which eliminate the stress induced peeling during CMP was demonstrated. Nanometer smoothness and a highly <111> texture of Cu can be achieved by optimizing the EP process. A 4-level Cu/low-k interconnect with CMP-less process was demonstrated with excellent yield. This process improves the throughput on ECP and CMP by two and has less dishing.
Electromigration reliability of dual damascene Cu/CVD SiOC interconnectsElectromigration (EM) characteristics were evaluated for multilevel copper test structures embedded in a CVD SiOC low k inter-metal dielectric. After electromigration stress testing, Cu extrusion along the interface between SiOC and the SiN dielectric diffusion barrier was revealed as the primary cause of EM failure. No evidence of cracking or mechanical weak points was observed in the bulk SiOC film; thus improved EM lifetime is expected from enhancement in the adhesion strength of SiN to SiOC. The calculated EM activation energies for 0.35 /spl mu/m via chains and 0.5 /spl mu/m via chains are 0.82 eV and 0.93 eV, respectively. The current density exponent (n) was measured to be about 1, which is consistent with the void growth mechanism in Cu. The critical length was found to decrease with increasing current density, and the j/spl middot/L/sub c/ product was determined to be approximately 7500 A/cm.
Film properties and surface profile after gap fill of electrochemically deposited Cu films by DC and pulse reverse processesThe self-annealing and the surface reflectivity of Cu films prepared by electrochemical deposition (ECD) are obtained for the DC and pulse reverse processes. They show different behaviors for these two processes, and their behaviors can be well correlated with the grain size of the films. The mechanism of gap fill is discussed according to the surface profile after gap fill for these two processes. It is proposed that the gap filling is mainly controlled by the additive diffusion for the DC process, while it is mainly controlled by the additive adsorption for the pulse reverse process.
Reliability of dual damascene Cu metallizationThe electromigration (EM) and bias temperature stress (BTS) performances of Cu metallization in dual damascene structure were examined. The experimental results show that Cu has more than one order of magnitude EM lifetime relative to Al alloy. The activation energy of electromigration of Cu trench is 0.9 eV. The failure sites of Cu dual damascene process after EM stress testing are mainly in the bottom of cathode site's vias. Via electromigration can be improved up to one order magnitude by optimizing several processes such as PR stripping, pad structure, etc. BTS study results indicate that the activation energy of Cu ion drift leakage is around 1.1 to 1.4 eV. The interface of capping SiN and SiO/sub 2/ was found to be the major copper diffusion path. Lifetime extrapolated from the empirical data indicates that the device can sustain longer than 1000 years under normal operation condition.
The evaluation of the diffusion barrier performance of reactively sputtered TaN/sub x/ layers for copper metallizationTa-based Cu diffusion barrier properties were widely studied. This work demonstrates that grain boundary diffusivity of Cu diffusion in various TaN/sub x/ (x=0/spl sim/0.62) thin films can be extracted from the copper concentration profile, based on the Whipple analysis of grain boundary diffusion, after annealing the samples at fixed temperatures between 200 and 500/spl deg/C. We used the grain boundary diffusivity to predict the penetration depth (2/spl radic/Dt) of Cu in Ta and TaN/sub x/ films at fixed temperatures 250 and 400/spl deg/C. Cu/TaN/sub x/(45 A)/N/sup +/P junction diode leakage, SIMS and XSEM analysis results indicated that the Whipple model correlates well with experimental results.
Interconnect is critically important for system performance. They are structures that connect two or more circuit elements (such as transistors) together electrically. In the past, interconnect was often referred to as on-chip interconnect of integrated circuits. Nowadays interconnect generally includes both on-chip interconnect of integrated circuits and off-chip interconnect in heterogeneous system integration. In interconnect design, geometric dimensions (width, thickness, spacing, aspect ratio, pitch), materials, process control and design layout are all critical to proper interconnect function, performance, power efficiency, reliability, and fabrication yield.