Interconnect

The electrical characterization of System on Integrated Chips (SoIC™), an innovative 3D heterogeneous integration technology manufactured in front-end of line with known-good-die is reported. Chiplets integration of devices including foundry leading edge 7nm FinFET technology with SoIC™ illustrates its advantages in high bandwidth density and high power efficiency, as compared with 2.5D and conventional 3D-IC with micro-bump/TSV.

From high-performance computing (HPC) applications such as Artificial Intelligence (A.I.) rising, advanced multi-chip packaging to integrate different functions could be a fast time-to-market and cost effective solution instead of SOC. Accordingly, more I/O die to die communications for advanced packaging is a need. To fulfill this demand, large number in registered routing lines between dies lead a constant drive for miniaturization for die to die Redistributed Layer (RDL) among industry. In this article, InFO Ultra-High-Density (UHD) RDL technology [1] is demonstrated, with RDL line-width down to submicron range (<;1um). This technology can empower the needs with industry trend. The InFO UHD RDL technology is characterized by electrical performances, e.g., via-chain continuity, RDL Comb/Meander Rs, line-to-line leakage current, and eventually reliability testing such as electro-migration (EM), stress migration (SM), breakdown voltage (Vbd), Time-Dependent-Dielectric Breakdown (TDDB), etc. After process optimization, the electrical test data demonstrate >99% yields from via-chain continuity, RDL Comb/Meander Rs and leakage current. Initial reliability testing shows good performance from EM, SM, Vbd, TDDB, etc. Package-level reliability test and results will also be addressed in this article. The potential challenges ahead will be discussed in terms of fundamental technical confinements as further scaling-down in RDL line-width and via, based on simulated and theoretical predictions, and possible approaches to resolve them.

The molded underfill (MUF) offers many unique advantages, including lower material costs, higher throughput, and excellent reliability for flip-chip chip scale packages (fcCSP) and fan-out packages. The assembly process yield and reliability of these packages are significantly influenced by the warpage behaviors of MUF. We develop an integrated process modeling approach incorporated with real-time chemical shrinkage and cure-dependent viscoelastic constitutive model for warpage prediction. The cure-dependent chemical shrinkage, kinetics and viscoelasticity are measured using pressure-volume-temperature (PVT) method, differential scanning calorimetry (DSC) and dynamic mechanical analysis (DMA). The integrated model is applied to fcCSP and fan-out packages with different designs, and the simulation results are in good agreement with the experimental data. A simplified model is also constructed for MUF with a fast corss-linking rate. In addition to warpage prediction, we successfully demonstrate that the model is useful to select suitable MUF baseline materials.

In the era of IoT, everything is connected through mutual data communication. System designers keep raising the bar for faster data transmission speed and wider data bandwidth to meet the ever-increasing data transmission demands from clouds computing such as data centers, servers, AI to edge devices such as mobile devices, AR/VRs, cars, robots, drone and so on. To resolve aforementioned huge data growth challenges, the next-generation advanced packaging solutions in 5G and RF mmWave communication become a very hot research topic among semiconductor industry as well as academic community. Particularly, how to provide a high density, high speed interconnect link with a minimized electrical transmission loss at high frequency becomes a critical R&D subject for packaging designers. In this paper, we demonstrated the first time a fine pitch, two-layers embedded Cu dual damascene RDLs with stacked vias on a 300 mm wafer using a single lithography dielectrics film. Each RDL layer composes of a sub-5 μm microvias and a 2 μm/1 μm line/ space (L/S) escape routing using a Cu dual damascene process. A liquid photoimageable dielectrics film was used for the fabrication of microvias and RDL trenches using a UV lithography tool. To achieve a good total thickness variation (TTV) control within the thin dielectrics film, a CMP process was applied to remove the plated Cu overburden and seed metal from the dielectrics surface while maintaining a smooth planarization surface to minimize the electrical transmission loss when system chips running at a high frequency. With demonstrated fine pitch, multi-layers Cu dual damascene RDLs, the existing wafer level fan-out SiP technologies can be readily extended to realize the next-generation high density, high performance advanced packaging in 5G and RF mmWave applications.

InFO_AiP technology, with low loss chip-to-antenna interconnect and wideband slot-coupled patch antenna, is proposed for low power, high performance, and compact 5G millimeter wave (mmWave) system integration. The low loss chip-to-antenna interconnect is related to low metal surface roughness of redistribution layer (RDL) and smooth interconnect transition between chip and package in InFO technology. The InFO RDL with low metal roughness results in transmission loss of 0.3 dB/mm which is lower than the loss of Cu trace on substrate, and the smooth interconnect transition with low discontinuity structure reduces the interconnect loss, by 0.78 dB at 60 GHz. A wideband slot-coupled patch antenna is designed successfully with 22.8% FBW (56.6-71.2GHz) and over antenna gain of 3 dBi in the operating band. To verify the technology performance, an InFO_AiP sample at 60 GHz is first designed, fabricated, and measured. The measurement result has a good agreement with the simulation and shows S11 ? -10 dB bandwidth of 55-65 GHz. As a result, InFO_AiP is a leading technology for 5G mmWave system application from power and performance considerations.

High performance millimeter wave passive devices are realized on smooth, fine pitch InFO redistribution layer (RDL). These passive devices are balun, power combiner, coupler, and microstrip line and the electrical performances are measured from 0.1GHz to 67 GHz through VNA. The measurement results show that the transmission loss of on-InFO balun (4.3 dB), the power divider (4.3 dB), and the coupler (4.9 dB) outperforms on-chip one by 2.1 dB, 1 dB, and 0.2 dB, respectively. While the transmission loss of microstrip line (0.34 dB/mm) is better than on-chip one by 0.17 dB/mm at 60 GHz. Furthermore, the parasitic of InFO chip-package interconnection has been investigated and compared to other technologies with and without solder bumps. The parasitic resistance, inductance, and capacitance for InFO interconnection are 75 %, 76 %, and 14 % lower than those for chip-last, face-down technology. Parasitic resistance for InFO RDL is 10 % lower than that for chip-first face-down technology with uneven RDL.

The viscoelastic behavior of the molding compound in fine pitch encapsulated electronic packages has a significant impact on component warpage and SMT assembly reliability. This is particularly true for the thin or ultra-thin (such as fan-out) packages used in mobile handsets and tablets, where process-induced warpage behavior is exacerbated by a larger molding volume and higher density of Cu trace layout. To ensure good assembly process yield and long term reliability, warpage relaxation during wafer molding process should be specially addressed and optimized with the effects of cure-dependent and time-domain viscoelastic relaxation from the molding material. In this paper, warpage evolution over the entire compression molding curing process, including compression molding cure (CMC) and the subsequent post molding cure (PMC), are characterized. An integrated process modeling approach using finite element (FE) method incorporated with the cure-dependent viscoelastic constitutive models of the molding material is successfully developed. The curing kinetics and viscoelastic behavior in the time domain of the molding material are characterized with differential scanning calorimetry (DSC) and dynamic mechanical analysis (DMA). Not only are the predicted warpage results based on the integrated process modeling approach in agreement with the in-line warpage measurement data, but this paper also finds that curing process conditions such as cure time, cure temperature, and curing stages can be used to tailor the warpage behaviors. The optimized curing conditions effectively improve the in-line warpage to enhance process yield and throughput.

Advanced heterogeneous integration (HI) technology is much needed for applications from edge to cloud to meet the stringent system-level requirements on performance, power, profile, cycle-time and cost (P3C2). In addition to 3DIC with TSV innovative packaging technologies such as silicon interposer (2.5D) and fan-out wafer-level-packaging (2D/3D) become new paradigm for the semiconductor industry to realize the system integration. In this paper, we will discuss the new trend of advanced packaging technology - a strong need for application-specific integration solutions. Many of those are proposed. The solution with higher performance at lower cost will prevail. Furthermore, the solutions that readily integrate multi-chip to enable chip-partition to extend Moore's Law effectively have long-term advantages.

Advanced heterogeneous integration (HI) technology is much needed for applications from edge to cloud to meet the stringent system-level requirements on performance, power, profile, cycle-time and cost (P3C2). In addition to 3DIC with TSV innovative packaging technologies such as silicon interposer (2.5D) and fan-out wafer-level-packaging (2D/3D) become new paradigm for the semiconductor industry to realize the system integration. In this paper, we will discuss the new trend of advanced packaging technology - a strong need for application-specific integration solutions. Many of those are proposed. The solution with higher performance at lower cost will prevail. Furthermore, the solutions that readily integrate multi-chip to enable chip-partition to extend Moore's Law effectively have long-term advantages.

State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200 mm 2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accommodate chips of logic and memory and achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approaches such as chip-on-substrate, CoWoS offers more competitive design rule which results in better power consumption, transmission loss, and eye diagram. CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.