High Performance, High Density RDL for Advanced PackagingIn the era of IoT, everything is connected through mutual data communication. System designers keep raising the bar for faster data transmission speed and wider data bandwidth to meet the ever-increasing data transmission demands from clouds computing such as data centers, servers, AI to edge devices such as mobile devices, AR/VRs, cars, robots, drone and so on. To resolve aforementioned huge data growth challenges, the next-generation advanced packaging solutions in 5G and RF mmWave communication become a very hot research topic among semiconductor industry as well as academic community. Particularly, how to provide a high density, high speed interconnect link with a minimized electrical transmission loss at high frequency becomes a critical R&D subject for packaging designers. In this paper, we demonstrated the first time a fine pitch, two-layers embedded Cu dual damascene RDLs with stacked vias on a 300 mm wafer using a single lithography dielectrics film. Each RDL layer composes of a sub-5 μm microvias and a 2 μm/1 μm line/ space (L/S) escape routing using a Cu dual damascene process. A liquid photoimageable dielectrics film was used for the fabrication of microvias and RDL trenches using a UV lithography tool. To achieve a good total thickness variation (TTV) control within the thin dielectrics film, a CMP process was applied to remove the plated Cu overburden and seed metal from the dielectrics surface while maintaining a smooth planarization surface to minimize the electrical transmission loss when system chips running at a high frequency. With demonstrated fine pitch, multi-layers Cu dual damascene RDLs, the existing wafer level fan-out SiP technologies can be readily extended to realize the next-generation high density, high performance advanced packaging in 5G and RF mmWave applications.
InFO_AiP Technology for High Performance and Compact 5G Millimeter Wave System IntegrationInFO_AiP technology, with low loss chip-to-antenna interconnect and wideband slot-coupled patch antenna, is proposed for low power, high performance, and compact 5G millimeter wave (mmWave) system integration. The low loss chip-to-antenna interconnect is related to low metal surface roughness of redistribution layer (RDL) and smooth interconnect transition between chip and package in InFO technology. The InFO RDL with low metal roughness results in transmission loss of 0.3 dB/mm which is lower than the loss of Cu trace on substrate, and the smooth interconnect transition with low discontinuity structure reduces the interconnect loss, by 0.78 dB at 60 GHz. A wideband slot-coupled patch antenna is designed successfully with 22.8% FBW (56.6-71.2GHz) and over antenna gain of 3 dBi in the operating band. To verify the technology performance, an InFO_AiP sample at 60 GHz is first designed, fabricated, and measured. The measurement result has a good agreement with the simulation and shows S11 ? -10 dB bandwidth of 55-65 GHz. As a result, InFO_AiP is a leading technology for 5G mmWave system application from power and performance considerations.
High Performance Chip-Partitioned Millimeter Wave Passive Devices on Smooth and Fine Pitch InFO RDLHigh performance millimeter wave passive devices are realized on smooth, fine pitch InFO redistribution layer (RDL). These passive devices are balun, power combiner, coupler, and microstrip line and the electrical performances are measured from 0.1GHz to 67 GHz through VNA. The measurement results show that the transmission loss of on-InFO balun (4.3 dB), the power divider (4.3 dB), and the coupler (4.9 dB) outperforms on-chip one by 2.1 dB, 1 dB, and 0.2 dB, respectively. While the transmission loss of microstrip line (0.34 dB/mm) is better than on-chip one by 0.17 dB/mm at 60 GHz. Furthermore, the parasitic of InFO chip-package interconnection has been investigated and compared to other technologies with and without solder bumps. The parasitic resistance, inductance, and capacitance for InFO interconnection are 75 %, 76 %, and 14 % lower than those for chip-last, face-down technology. Parasitic resistance for InFO RDL is 10 % lower than that for chip-first face-down technology with uneven RDL.
Warpage Modeling and Characterization of the Viscoelastic Relaxation for Cured Molding Process in Fan-Out PackagesThe viscoelastic behavior of the molding compound in fine pitch encapsulated electronic packages has a significant impact on component warpage and SMT assembly reliability. This is particularly true for the thin or ultra-thin (such as fan-out) packages used in mobile handsets and tablets, where process-induced warpage behavior is exacerbated by a larger molding volume and higher density of Cu trace layout. To ensure good assembly process yield and long term reliability, warpage relaxation during wafer molding process should be specially addressed and optimized with the effects of cure-dependent and time-domain viscoelastic relaxation from the molding material. In this paper, warpage evolution over the entire compression molding curing process, including compression molding cure (CMC) and the subsequent post molding cure (PMC), are characterized. An integrated process modeling approach using finite element (FE) method incorporated with the cure-dependent viscoelastic constitutive models of the molding material is successfully developed. The curing kinetics and viscoelastic behavior in the time domain of the molding material are characterized with differential scanning calorimetry (DSC) and dynamic mechanical analysis (DMA). Not only are the predicted warpage results based on the integrated process modeling approach in agreement with the in-line warpage measurement data, but this paper also finds that curing process conditions such as cure time, cure temperature, and curing stages can be used to tailor the warpage behaviors. The optimized curing conditions effectively improve the in-line warpage to enhance process yield and throughput.
Advanced Heterogeneous Integration Technology Trend for Cloud and EdgeAdvanced heterogeneous integration (HI) technology is much needed for applications from edge to cloud to meet the stringent system-level requirements on performance, power, profile, cycle-time and cost (P3C2). In addition to 3DIC with TSV innovative packaging technologies such as silicon interposer (2.5D) and fan-out wafer-level-packaging (2D/3D) become new paradigm for the semiconductor industry to realize the system integration. In this paper, we will discuss the new trend of advanced packaging technology - a strong need for application-specific integration solutions. Many of those are proposed. The solution with higher performance at lower cost will prevail. Furthermore, the solutions that readily integrate multi-chip to enable chip-partition to extend Moore's Law effectively have long-term advantages.
Advanced heterogeneous integration technology trend for cloud and edgeAdvanced heterogeneous integration (HI) technology is much needed for applications from edge to cloud to meet the stringent system-level requirements on performance, power, profile, cycle-time and cost (P3C2). In addition to 3DIC with TSV innovative packaging technologies such as silicon interposer (2.5D) and fan-out wafer-level-packaging (2D/3D) become new paradigm for the semiconductor industry to realize the system integration. In this paper, we will discuss the new trend of advanced packaging technology - a strong need for application-specific integration solutions. Many of those are proposed. The solution with higher performance at lower cost will prevail. Furthermore, the solutions that readily integrate multi-chip to enable chip-partition to extend Moore's Law effectively have long-term advantages.
Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS TechnologyState-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200 mm 2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accommodate chips of logic and memory and achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approaches such as chip-on-substrate, CoWoS offers more competitive design rule which results in better power consumption, transmission loss, and eye diagram. CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.
Advance Patterning Approach for Cu/Low-k interconnectsThe RC delay, electro migration (EM) and TDDB performance become more challenges to meet device requirement as continuous geometry shrink on BEOL dual damascene interconnects. To overcome these challenges from interconnect patterning point of view, we proposed Cu subtractive RIE as a potential solution for next generation Cu/Low-k interconnects.
Ultra-thin ALD-MnN Barrier for Low Resistance Advanced Interconnect TechnologyAs dimension shrinks the volume percent occupied by conventional barrier and liner increases and line resistance (Rs) and via resistance (Rc) increases dramatically. An ultrathin ALD MnN barrier is being evaluated as a single layer barrier for resistance reduction in small structures. >20% and >80% Rs and Rc reduction was demonstrated, while 4× better mean time to failure (MTTF) on the time dependent dielectric breakdown (TDDB) was achieved comparing to conventional barrier/liner. ALD MnN is a potential barrier candidate for future interconnects technology.
CPI advancement in integrated fan-out (InFO) technologyAdvanced mobile computing devices nowadays demand for ever-increasing functionality, performance and bandwidth. The complexity of functional integration in mobile device has made it more challenging for wire bond and C4 bump flip chip packaging to meet the requirement of high I/O count and high density integration. Moreover, the extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) must be utilized to meet performance requirements from the advanced silicon technology nodes. In this paper, the maximum ELK stress for advanced mobile SoC integrated by different packaging technologies, aka integrated fan-out (InFO), chip last fan-out wafer level package (CL-FOWLP), and flip chip package, were evaluated by FEA first. Then the governing mechanisms behind the ELK stress were analyzed. The InFO outperforms CL-FOWLP and flip chip package in the maximum ELK stress due to its simplified architecture and fabrication process. With a low ELK stress, InFO technology can play an important role in enabling more advanced mobile ICs and high performance SoC packaging for the future 4C applications.
Interconnect is critically important for system performance. They are structures that connect two or more circuit elements (such as transistors) together electrically. In the past, interconnect was often referred to as on-chip interconnect of integrated circuits. Nowadays interconnect generally includes both on-chip interconnect of integrated circuits and off-chip interconnect in heterogeneous system integration. In interconnect design, geometric dimensions (width, thickness, spacing, aspect ratio, pitch), materials, process control and design layout are all critical to proper interconnect function, performance, power efficiency, reliability, and fabrication yield.