Interconnect

Chip-on-Wafer-on-Substrate (CoWoS-S) is a TSV-based multi-chip integration technology that has been in production for close to 10 years. It is widely used in high performance computing (HPC) and artificial intelligence (AI) accelerator area due to its flexibility to accommodate multiple chips of SoC, chiplet, and 3D stacks such as high bandwidth memory (HBM). The interposer size increases steadily over the past few years, from one full reticle size (~830 mm2) to two reticle size (~1700 mm2). The growth of interposer size offers more integration power to accommodate more active silicon in a package to satisfy the HPC/AI needs. In this paper, we report the new 5th generation CoWoS-S (CoWoS-S5) based on a Si interposer at three full reticle size (~2500 mm2) by a novel mask stitching approach. This will accommodate simultaneously multiple logic chips at a total area of 1200 mm2 (with chiplets) together with eight HBM stacks. In addition to dimensional increase in the Si interposer, new features are incorporated in the system to further enhance the electrical and thermal performances of CoWoS-S5 compared with the previous CoWoS-S portfolio. These include a 2nd generation integrated capacitor (iCap) for further enhanced power integrity, 5 layers of sub-micron Cu interconnect with lower sheet resistance to satisfy high speed die to die interconnect, new TSV structure interposer for both return and insertion loss reduction with good package reliability, and a higher thermal conductivity thermal interface material (TIM) to achieve a lower thermal resistance. Component level reliability with excellent electrical and physical results are also discussed.

This work shows a system for power delivery network (PDN) impedance measurements (PIM), targeting high-performance computing (HPC) applications. A delay-line based "TRIG-after-SAMP" approach relaxes timing margins and eliminates high-speed clock sources. On-chip DUTs, with two bonding schemes and a programmable de-coupling capacitor array, are demonstrated using 7nm FinFET technology. Measurement results show that this system achieves a sampling bandwidth of 27 GHz, an accuracy of 1 mV, and a core area of 0.028 mm2.

An array-based test-vehicle for tracking bit-error-rate (BER) degradation of signal interconnects subject to DC electromigration (EM) stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. BER measurement results from four individual interconnect paths are presented and analyzed.

A direct silicon water cooling solution using fusion bonded silicon lid is proposed. It is successfully demonstrated as an effective cooling solution with total power >2600 W on a single SoC, equivalent to power density of 4.8 W/mm2. Low temperature logic chip to silicon lid fusion bonding, with trench/grid cooling structure cutting into silicon lid enables minimal thermal resistance between active device and cooling water and best cooling efficiency. Direct water cooling on logic chip silicon backside has also been demonstrated with power density better than 7 W/mm2.

A direct silicon water cooling solution using fusion bonded silicon lid is proposed. It is successfully demonstrated as an effective cooling solution with total power >2600 W on a single SoC, equivalent to power density of 4.8 W/mm2. Low temperature logic chip to silicon lid fusion bonding, with trench/grid cooling structure cutting into silicon lid enables minimal thermal resistance between active device and cooling water and best cooling efficiency. Direct water cooling on logic chip silicon backside has also been demonstrated with power density better than 7 W/mm2.

Fan-out wafer level package (FOWLP) is a disruptive technology in the semiconductor packaging industry. Demand for higher system performance has caused an increase in both package size and the complexity of heterogeneous integration. Large warpage, which arises from significant volume changes in molded underfill (MUF) during the curing and subsequent assembly processes, is a top process and reliability issue. The selection of molding material is critical importance in FOWLP, as the material must meet multiple manufacturing requirements. In this study, an integrated modeling approach is used to predict wafer form warpage of fan-out packages. This approach considers both chemical shrinkage and cure dependency of molded underfill. Viscoelastic relaxation behavior over the course of compression molding curing (CMC) and subsequent post-molding curing (PMC) has been carefully modeled. Measurements of material properties used in our models were characterized through differential scanning calorimetry (DSC) and dynamic mechanical analysis (DMA). The result of our integrated modeling approach was validated by comparing actual warpage data of various temperature loading conditions. Predicted warpage values are in good agreement with in-line experimental data. Furthermore, we apply this methodology to study the wafer fan-out ratio and Cu density effect. It is shown that Cu density effect is not sensitive, and higher wafer fan-out ratio induces larger warpage due to more molding volume.

An advanced 3D Multi-stack (MUST) system integration technology, 3D MUST-in-MUST (3D-MiM) fan out package, has been developed as next generation wafer-level fan-out package technology. 3D-MiM technology utilizes a more simplified architecture which eliminates BGAs between packages for system-level performance, power and form-factor (PPA) purpose. This technology also makes use of a modularized approach for both design and integration flow to improve design flexibility and integration efficiency. Known-good pre-stacked memory cube and/or logic-memory cubes are fabricated by leveraging the established integrated fan-out technology platform (InFO) in tools, materials, design rules, and processes to shorten development cycle time and achieve cost effectiveness. Two 3D-MiM fan-out examples are presented in this paper. The first 3D-MiM package integrates a SoC with 16 memory chips in a 15 × 15 mm 2 footprint with 0.5 mm package height (final BGA included) for mobile application. The other 3D-MiM package integrates 8 SoCs with 32 memory chips in a 43 × 28 mm 2 footprint to mimic a system integration of multiple logic cores and multiple memory chips for HPC applications.

Heterogeneous integration has attracted much attention for high performance computing (HPC) since artificial intelligence (AI) accelerators surged. The technologies for heterogeneous integration, such as silicon interposer (2.5D), fan-out wafer-level-packaging (FOWLP), and organic substrate, have been proposed to integrate logic-logic or logic-HBM chips in the AI system for performance and cost benefits. However, the tremendous data flow in 5G era requires higher data rate and bandwidth for the extensive die-to-die communication. Therefore, a BEOL-scale re-distributed layer (RDL) technology should be developed to satisfy the requirements. In this paper, a novel ultra-high-density InFO (InFO_UHD) technology with submicron RDL is developed to provide high interconnect density and bandwidth for logic-logic system. The bandwidth density can achieve record high 10 Tbps/mm at line width and spacing (L/S) of 0.8/0.8 um and length of 500 um, for a logic-logic system using simplified IO driver. Using the technology in logic-memory system, we found that the scaling of RDL thickness, L/S, and dielectric thickness can mitigate ring-back problems in the eye diagram of organic substrate. Given HBM2 specification, the bandwidth density can achieve more than 0.4 Tbps/mm from dramatically improved signal integrity. Finally, power efficiency, in the metric of energy per bit, of the interconnect technology under simplified IO driver and HBM2 driver condition was calculated and compared with other technology, respectively.

A brand new 3D integrated circuit (3DIC) solution, System on Integrated Chips (SoIC™), has been successfully developed to integrate active and passive chips into a new integrated SoC system to meet ever-increasing market demands on higher computing efficiency, wilder data bandwidth, higher functionality packaging density, lower communication latency, and lower energy consumption per bit data. 3D packaging is challenging and requires overcoming three major challenges - thermal, power delivery, and yield. The SoIC, as industry-first 3D logic-on-logic and memory-on-logic chiplet stacking technology platform, enables the heterogeneous integration (HI) of known good dies (KGDs) with different chip sizes, functionalities and wafer node technologies, all to be integrated in a single, compact new system chip. From external appearance, SoIC looks like a general SoC chip with multiple pre-designed heterogeneous functional chips embedded. As SoIC is fabricated using "front-end" process, it can be holistically integrated into variant "back-end" advanced packaging technology platforms such as flip chip, integrated fan-out (aka InFO), 3DIC, and 2.5D with Si interposer (e.g. CoWoS™) [1-2] to provide a miniaturized and highly integrated HI SiP for the future HPC, AI, 5G, and edge computing applications. With the innovative bonding scheme, SoIC enables the strong bonding pitch scalability for chip I/O to realize a high density die-to-die interconnects. The bond pitch starts from sub-10 μm rule. Short die-to-die connection of SoIC has the merits of smaller form-factor, higher bandwidth, better power integrity (PI), signal integrity (SI), and lower power consumption comparing to the current industry state-of-the-art packaging solutions. In this paper, we demonstrated for the first time an integration of SoIC chip into InFO_PoP without increasing its form-factor. The SoIC was made on a logic-on-logic stacking to validate the design rules, process maturity, and reliability.

Board level reliability during drop impact is a major concern for electronic packages. The impact force generated as the casing strikes the ground can cause electronic device failures in handheld products. The full drop testing procedure is costly and time-consuming due to complex sample preparation and test set-up procedures. Failure analysis also requires significant manpower to conduct. Therefore, an impact modeling method to predict the results of board level drops is highly desirable. We propose a dynamic modeling approach to describe the transient response of the package during impact based on an Input-G loading method with an implicit solver algorithm. The dynamic response of an ultra-thin package is obtained experimentally using a drop tester with accelerometer, strain gauge, and resistance monitor. For the Input-G method, the acceleration response of the impact pulse is then converted into a velocity form, and is taken as the loading input to a finite element (FE) model in this paper. The time dependent PCB strain, spectrum analysis, and modal analyses are used to correlate with the FE model and used to understand drop impact behaviors. Spectra of impact pulse and PCB dynamic strains are obtained by using the Fast Fourier Transform (FFT) technique. The extracted bending shape and frequency are consistent with the modal analysis results. The bending shape is mainly determined by the first mode. Knowledge about the spectra of PCB dynamic responses are required to understand the bending characteristics, which affect the package drop reliability. This FE model provides an accurate and reliable way to understand failure physics, and to help to achieve service life improvements in early development stage.