Logic

Narrow 〈110〉Si oriented trenches with high aspect ratio served as template to grow Ge on Si (001) substrate. Cross section high resolution transmission electron microscopy reveals a high crystalline quality relaxed Ge inside the trench with only a few structural defects in the vicinity of a well ordered misfit dislocation grid at the Ge/Si interface. These dislocations are formed along the 〈111〉Ge lattice planes and terminate in the first 20 nm of grown Ge. The high structural Ge quality is maintained both parallel and perpendicular to the trench as was confirmed by additional plan view and cross section inspections along the trench.

Measurements made on heavily doped n-channel accumulation-mode planar metal-oxide-semiconductor field-effect transistors (MOSFETs) reveal that the channel mobility can reach values significantly higher than the bulk mobility at the same doing level. This effect is attributed to a screening effect: in the accumulation channel, the high concentration of the majority carriers brings about an electrostatic screening effect that reduces impurity coulomb scattering. As a result, mobility values that can reach twice the value expected in the bulk material are observed in the accumulation channel.

We report an ultrashallow metallic source/drain (S/D) contact scheme for fully self-aligned III-V NMOS with specific contact resistivity and sheet resistance which, for the first time, demonstrate performance metrics that may be compatible with the ITRS R ext requirements for 12-nm technology generation device pitch. The record specific contact resistivity between the contact pad and metallic S/D of ρ c = 2.7 ·10 -9 Ω·cm 2 has been demonstrated for 10 nm undoped InAs channels by forming an ultrashallow crystalline ternary NiInAs phase with R sh = 97 Ω/sq for a junction depth of 7 nm. The junction depth of the S/D scheme is highly controllable and atomically abrupt.

We report the first demonstration of scaled Ge p-channel FinFET devices fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [1]. Excellent subthreshold characteristics (long-channel subthreshold swing SS=76mV/dec at 0.5V), good SCE control and high transconductance (1.2 mS/μm at 1V, 1.05 mS/μm at 0.5V) are achieved. The Ge FinFET presented in this work exhibits highest g m /SS at V dd =1V reported for non-planar unstrained Ge pFETs to date.

Stress-Memorization-Technique by Si dislocations is effective in enhancing NFET device performance [1,2]. For the first time, MD (Molecular Dynamic) simulations are applied to explain the formation mechanism of dislocations during the Solid-Phase-Epitaxy-Regrowth (SPER) process. A semi- empirical TCAD method based on lattice-KMC (L-KMC) is then developed to predict dislocation formation. The simulated dislocation positions agree well with silicon experiments characterized by TEM. TCAD simulations show that the resulting dislocations are along the [111] direction and provide ~650MPa average longitudinal stress in channel regions, consistent with Nano-Beam-Diffraction (NBD) strain measurement. The channel stress is predicted by simulation to further increase by 1.5X after the poly-silicon gate removal step in a replacement-gate process. The dislocation SMT enhances NFET electron mobility by 25% and Ion-Ioff performance by 15%.

The growth and bonding chemistry at a gate dielectric Ga2O3/GaAs interface is investigated using in-situ photoemission techniques. A multi-chamber molecular beam epitaxy/analysis system allows for the controlled deposition of III–V and oxide layers and the probing of these layers without exposure to atmosphere. The growth of Ga2O3 on a (2×4) reconstructed GaAs surface proceeds with molecules of Ga2O insertion into pairs of As-dimers with the surface void of As–O bonding. Subsequent growth involved the combination of Ga2O with oxygen to form Ga2O3. However, for stoichiometric Ga2O3, the substrate temperature >440 °C is required to provide the necessary energy for the reaction. This growth process is unique and represents a method for unpinning the Fermi level for GaAs with a low level of interface state density required for the fabrication of enhancement mode MOSFET devices.

An industry leading 28nm high-performance mobile SoC technology featuring metal-gate/high-k process is presented. The technology is optimized to offer wide power-to-performance transistor dynamic range and highest wired gate density with superior low-R/ELK interconnects, critical for next generation mobile computing/SOC applications. Through process and design optimization, historical trend is maintained for gate density and SRAM cell sizes. Variations control strategy through process and design collaboration is also described.

A classification scheme for III-V MOSFETs for future CMOS is proposed and n-channel devices are benchmarked both within the group of III-V MOSFETs and in comparison with state-of-the-art silicon MOSFETs. Metrics which are based on the first derivative of drain current (I d ) vs gate voltage (V gs ) are found to be most suitable for benchmarking technologies of widely diverging maturity level. Although recently reported III-V MOSFETs exhibit markedly improved performance, they still lag state-of the-art Si MOSFETs. However, Schottky gate III-V devices with an InAs channel layer already outperform silicon MOSFETs today.

We present a novel calibration methodology that (i) integrates dopant diffusion, mechanical strain and bandgap narrowing for accurate device short channel effect modeling and (ii) deploys stress dependent mobility model for robust device performance projection especially on effective drive current (Ideff). Good agreement is obtained between the model calibration and experimental measurements over the full gate length range examined. Moreover, a general mobility gain with respect to uniaxial stress is presented.

This paper presents a BSIM-based method for source/drain series resistance and mobility extraction in nanoscale strained-silicon metal oxide semiconductor field effect transistors (MOSFETs) with halo implants. This method is more accurate than the conventional channel-resistance and shift and ratio method because it considers the gate-length dependence of mobility caused by local uniaxial stress and laterally nonuniform channel doping. We have verified this method using samples with different stressor/doping conditions and good agreement with experimental data has been obtained. The accuracy of the Berkeley Short-channel IGFET model (BSIM) extraction method is also proven by simulated current–voltage characteristics with different external resistant values. Significant mobility degradation in the short-channel regime has been observed for various uniaxial stressors. This method may serve as a suitable process monitor tool for ultrashallow junction and strained process development.