TSMC has been at the forefront of advanced CMOS logic technologies for which dense transistors are one of the two essential building blocks, the other being dense interconnect stacks. The intrinsic computing capability of a given logic technology is directly related to the number of interconnected transistors and their switching speed under representative loads originating from both the transistor or gates being driven and the related interconnect resistive and capacitive circuit loads.

TSMC research and development is continuously exploring novel and scalable transistor concepts to ensure sustainable, cost-effective, leading-edge logic technology performance and energy efficiency. We invite you to explore some of TSMC research areas in transistor structure, high-mobility channel, and low-dimensional materials and devices.

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  • Low power device technology with SiGe channel, HfSiON, and poly-Si gate

    We report solutions to the formidable challenges posed by integrating a HfSiON dielectric with a poly-Si gate for low-power device technology. A 1.5 nm EOT HfSiON is demonstrated with mobility comparable to SiO/sub 2/ and 3 orders of magnitude leakage reduction. A novel boron delta-doped strained-SiGe channel points a way out of the high threshold voltage problem associated with Fermi-pinning at the high-k/poly-Si interface and ameliorates short-channel effects in PMOS devices. In addition, a 20% hole mobility enhancement and 15% I/sub on/-I/sub off/ characteristics improvement are achieved owing to the compressive SiGe channel. NMOS PBTI lifetime of 35 years, and PMOS NBTI and NMOS hot carrier lifetimes of more than 1000 years are demonstrated at 1.2 V.
  • Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65 nm CMOS Scaling

    A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.
  • Study on STI mechanical stress induced variations on advanced CMOSFETs

    Impact of shallow trench isolation (STI) induced mechanical stress on MOSFET drive current is investigated by means of a full-matrix active area layout experiment in advanced CMOS process technology. It turns out remarkably that transistor drive current density per unit width is not independent of the active area size, particularly along the direction of the channel current flow. Opposite sensitivities are observed between n- and p-MOSFETs with respect to lateral active area size. The role of gate placement inside the active area is also addressed. A statistical analysis scheme to find principal components is carried out as well.
  • CMOS technology for MS/RF SoC

    Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to mixed-signal/radio-frequency (MS/RF) segments. Improvements in device speed, matching, and minimum noise figure are all consistent with fundamental scaling trends. Other figures-of-merit such as linearity and 1/f noise do not scale favorably but are not considered to be roadblocks when viewed from a circuit design perspective. Furthermore, interconnect architectural scaling trends in logic technology have facilitated improvements in passive-component performance metrics. These improvements compounded with innovations in circuit design have made CMOS technology the primary choice for cost driven MS/RF applications. This paper reviews active and passive elements of CMOS MS/RF system-on-chip (SoC) technology from a scaling perspective. The paper also discusses the implications that physical phenomena such as mechanical stress and gate leakage as well as gate patterning have on technology definition and characterization.
  • Junction engineering and modeling for advanced CMOS technologies

    This paper discusses an integrated modeling approach for diffusion profiles in advanced CMOS technologies. First, for USJ (Ultra-Shallow Junction) arsenic modeling, in addition to a fully-coupled model with implant damage, amorphous layer formation which depends on the Frenkel pair concentration and evolution of (311) defects and dislocation loops based on EOR (End of Range) defects are also used. Secondly, in order to improve polysilicon activation, a hybrid (arsenic + phosphorus) Source/Drain is used for NMOS. We also address the calibration of the hybrid Source/Drain for with various anneal temperatures. It is shown that modeling of the hybrid Source/Drain profile can be achieved by optimization of the dopant's Fermi level dependent diffusivity and the initial value of the point defect concentration in the equilibrium state. Finally, uphill diffusion at low anneal temperature is observed for BF2 USJ and is enhanced with Ge pre-implants. It is caused by a steep interstitial gradient created by preamorphisation and EOR damage, ultra-shallow boron profile, and boron long-hop diffusion. A BIC (Boron-Interstitial Cluster) model is employed to model boron diffusion after a spike RTA at both extension and S/D regions.
  • Impact of STI mechanical stress in highly scaled MOSFETs

    Intensive experiment on highly scaled MOSFETs with mask gate lengths down to 90 nm shows significant sensitivities (up to 10%) of drive current per unit width to the shrinking of active area size down to 0.6 /spl mu/m as well as to the gate placement distance from STI (shallow trench isolation) edge. This suggests the impact of STI induced mechanical stress along the direction of the channel current flow. Even n-and p-channel FETs are observed to behave in opposite trends with respect to the lateral active area size. Mechanical stress simulation of underlying entire front-end process line is conducted also intensively. Systematic analysis turns out strikingly that the experimental drive current sensitivity tracks well the compressive-type strain along the channel, leading to a correlation established between the two. This work promises exploration of mechanical stress issues in future nanoscale devices and circuits.
  • A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

    This paper demonstrates a new compact and scaleable model of mechanical stress effects on MOS electrical performance, induced by shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.
  • Foundry technology for 130nm and beyond SoC

    Current foundry technology menus are so rich that they are sufficient to provide single chip solutions to a wide variety of desktop, portable and communication systems. At 130-nm and 90-nm generations, many of the device characteristics are no longer a straightforward extension of past generations. Special attention should be made for mixed-signal chip design. A judicious choice of devices and careful trade-off between version options should be made to maximize the benefit from the latest foundry offerings.
  • A 65nm Node Strained SOI Technology with Slim Spacer

    A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.
  • Bulk CMOS technology for SOC

    CMOS technology scaling has come to a point whereby traditional assumptions that warranted a fair degree of de-coupling between process development and circuit/system design do not hold. One specific example relates to chip standby leakage. Today's most advanced transistor designs push gate dielectric thickness into a regime where direct tunneling currents are no longer negligible. Meanwhile, the portable electronics sector had become a key industry driver demanding VLSI circuits with ever increasing functionality-performance needs while maintaining tight controls on power consumption. To conciliate the scaling-driven technology fundamental limitations with the industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize Systems on a Chip (SoC). This paper discusses aspects of bulk CMOS SoC technology definition and front-end scaling trends.
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