Off-chip Interconnect

Silicon interposer, high-density fine-pitch fan-out RDL and bumpless bond are the three pillars of chip-to-chip interconnect on innovative advanced heterogeneous integration technologies (HIT). Each interconnect technology provides the best PPACC in their own domains of AI and 5G networks, and is tightly associated with a wafer-level heterogeneous integration technology, namely CoWoS, InFO and SoIC, respectively, in HPC and mobile application systems.

TSMC’s off-chip interconnect technologies continues to advance for better PPACC:

  1. Silicon interposer: high interconnect density, high specific capacitance density, and large reticle size for exascale HPC/AI
  2. Fan-out: high interconnect density and large reticle size in fan-out for cost and performance in HPC/network AI
  3. SoIC: high 3D interconnect density with ultra-low bonding latency for energy efficient computing systems

Note: PPACC: Power consumption, Performance, Area (form factor), Cost, Cycle time to market

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  • An ultra-thin interposer utilizing 3D TSV technology

    To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200 μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer.
  • Advanced Reliability Study of TSV Interposers and Interconnects for the 28nm Technology FPGA

    TSV interposer has emerged as a good solution to provide high wiring density interconnections, improved electrical performance due to shorter interconnection from the die to substrate, and minimized CTE mismatch between the chip and copper filled TSV interposer, resulting in high reliability micro bumps and more reliable low-k chip. Furthermore, for an interposer that does not contain any active device, already established process technology could be applied, TSV pitch could be coarser and a thicker interposer could be used. This paper presents the development of TSV interposer technology for a high-performance 28nm logic die that is mounted on a large silicon interposer with Cu through silicon via. A representative silicon interposer test chip with thousands of micro-bumps at 45um pitch has been fabricated. The silicon interposer is 100um thick, and is mounted on a 42.5mm×42.5mm substrate through 180um pitch C4 bumps. TSV fabrication process steps and assembly process of the large logic die mounted on the TSV interposer with lead-free micro-bumps have been optimized as well as assembly of the component on the organic substrate. 3D thermal-mechanical modeling and simulation for the packaged device with TSV interposer have been performed. The samples have been subjected to thermal cycling, electro-migration and moisture sensitivity tests. Effect of TSV interposer on the stress of the die, low-k layers and fatigue life of micro bumps and C4 bumps have been investigated. Several DOEs have been performed to optimize design and material selection in order to maximize yield and reliability. Finally, Si interposer seemed to be a low-risk 3D path to have a reliable package with acceptable warpage/coplanarity, passing 1000TCB without any crack, delamination or void being detected in low-k, TSV, micro bumps and C4 bumps.
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