Interconnect

High performance millimeter wave passive devices are realized on smooth, fine pitch InFO redistribution layer (RDL). These passive devices are balun, power combiner, coupler, and microstrip line and the electrical performances are measured from 0.1GHz to 67 GHz through VNA. The measurement results show that the transmission loss of on-InFO balun (4.3 dB), the power divider (4.3 dB), and the coupler (4.9 dB) outperforms on-chip one by 2.1 dB, 1 dB, and 0.2 dB, respectively. While the transmission loss of microstrip line (0.34 dB/mm) is better than on-chip one by 0.17 dB/mm at 60 GHz. Furthermore, the parasitic of InFO chip-package interconnection has been investigated and compared to other technologies with and without solder bumps. The parasitic resistance, inductance, and capacitance for InFO interconnection are 75 %, 76 %, and 14 % lower than those for chip-last, face-down technology. Parasitic resistance for InFO RDL is 10 % lower than that for chip-first face-down technology with uneven RDL.

The viscoelastic behavior of the molding compound in fine pitch encapsulated electronic packages has a significant impact on component warpage and SMT assembly reliability. This is particularly true for the thin or ultra-thin (such as fan-out) packages used in mobile handsets and tablets, where process-induced warpage behavior is exacerbated by a larger molding volume and higher density of Cu trace layout. To ensure good assembly process yield and long term reliability, warpage relaxation during wafer molding process should be specially addressed and optimized with the effects of cure-dependent and time-domain viscoelastic relaxation from the molding material. In this paper, warpage evolution over the entire compression molding curing process, including compression molding cure (CMC) and the subsequent post molding cure (PMC), are characterized. An integrated process modeling approach using finite element (FE) method incorporated with the cure-dependent viscoelastic constitutive models of the molding material is successfully developed. The curing kinetics and viscoelastic behavior in the time domain of the molding material are characterized with differential scanning calorimetry (DSC) and dynamic mechanical analysis (DMA). Not only are the predicted warpage results based on the integrated process modeling approach in agreement with the in-line warpage measurement data, but this paper also finds that curing process conditions such as cure time, cure temperature, and curing stages can be used to tailor the warpage behaviors. The optimized curing conditions effectively improve the in-line warpage to enhance process yield and throughput.

Advanced heterogeneous integration (HI) technology is much needed for applications from edge to cloud to meet the stringent system-level requirements on performance, power, profile, cycle-time and cost (P3C2). In addition to 3DIC with TSV innovative packaging technologies such as silicon interposer (2.5D) and fan-out wafer-level-packaging (2D/3D) become new paradigm for the semiconductor industry to realize the system integration. In this paper, we will discuss the new trend of advanced packaging technology - a strong need for application-specific integration solutions. Many of those are proposed. The solution with higher performance at lower cost will prevail. Furthermore, the solutions that readily integrate multi-chip to enable chip-partition to extend Moore's Law effectively have long-term advantages.

Advanced heterogeneous integration (HI) technology is much needed for applications from edge to cloud to meet the stringent system-level requirements on performance, power, profile, cycle-time and cost (P3C2). In addition to 3DIC with TSV innovative packaging technologies such as silicon interposer (2.5D) and fan-out wafer-level-packaging (2D/3D) become new paradigm for the semiconductor industry to realize the system integration. In this paper, we will discuss the new trend of advanced packaging technology - a strong need for application-specific integration solutions. Many of those are proposed. The solution with higher performance at lower cost will prevail. Furthermore, the solutions that readily integrate multi-chip to enable chip-partition to extend Moore's Law effectively have long-term advantages.

State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200 mm 2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accommodate chips of logic and memory and achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approaches such as chip-on-substrate, CoWoS offers more competitive design rule which results in better power consumption, transmission loss, and eye diagram. CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.

Advanced mobile computing devices nowadays demand for ever-increasing functionality, performance and bandwidth. The complexity of functional integration in mobile device has made it more challenging for wire bond and C4 bump flip chip packaging to meet the requirement of high I/O count and high density integration. Moreover, the extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) must be utilized to meet performance requirements from the advanced silicon technology nodes. In this paper, the maximum ELK stress for advanced mobile SoC integrated by different packaging technologies, aka integrated fan-out (InFO), chip last fan-out wafer level package (CL-FOWLP), and flip chip package, were evaluated by FEA first. Then the governing mechanisms behind the ELK stress were analyzed. The InFO outperforms CL-FOWLP and flip chip package in the maximum ELK stress due to its simplified architecture and fabrication process. With a low ELK stress, InFO technology can play an important role in enabling more advanced mobile ICs and high performance SoC packaging for the future 4C applications.

Steady-state and transient thermal performance of a novel memory-integrated 3D-stacking packaging technology, integrated fan-out package-on-package (InFO_PoP), developed for state-of-the-art mobile applications were experimentally characterized using a specially designed thermal test vehicle. Two competing technologies, flip-chip PoP (FC_PoP) and 3DIC, are also included in this study as the reference for thermal performance benchmark. Direct thermal performance comparison is made possible by the data collected on the comparable FC_PoP thermal test vehicles. Thermal models have been successfully developed to enable further study on the cross-package performance comparison, as well as the impact of various key package design parameters. With the innovative approach replacing the organic substrate with thermally favorable RDL layers, a typical InFO_PoP package has 12% and 17% lower junction-to-ambient thermal resistance than a typical FC_PoP and 3DIC package, respectively. The appealing transient thermal response also makes the InFO_PoP the most competitive 3D packaging technology in high-performance mobile applications. Although the strong thermal interactions between the component packages of a PoP package complicates the thermal analysis, power envelop is proposed and demonstrated as a useful tool for package thermal design optimization. In addition, transient thermal analysis is recommended as a supplementary thermal design approach to the commonly used steady-state thermal analysis.

A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices. This novel InFO technology is the first high performance Fan-Out Wafer Level Package (FO_WLP) with multi-layer high density interconnects proposed to the industry. In this paper we present the detailed comparison of InFO packages on package (InFO_PoP) with several other previously proposed 3D package solutions. Result shows that InFO_PoP has more optimized overall results on system performance, leakage power and area (form factor) than others, to meet the ever-increasing system requirements of mobile computing. InFO technology has been successfully qualified on package level with robust component and board level reliability. It is also qualified at interconnect level with high electromigration resistance. With its high flexibility and strong capability of multi-chips integration for both homogeneous and heterogeneous sub-systems, InFO technology not only provides a system scaling solution but also complements the chip scaling and helps to sustain the Moore's Law for the smart mobile as well as internet of things (IoT) applications.

A novel integrated fan-out package on package (InFO_PoP) technology for application processor (AP), memory, and PMIC system is developed for next generation high performance mobile applications. For AP and memory system, the InFO_PoP technology can provide better system performance and lower package profile, compared to current flip-chip package on package (FC_PoP) technology. For signal integrity, the eye height of eye diagram for the InFO_PoP is 24% larger than that for the FC_PoP at LPDDR4. For power integrity, the PDN impedance for the InFO_PoP is 84% lower than that for the FC_PoP at high frequency because of thinner dielectric layer between power/ground planes and shorter path from AP pad to PCB. For AP and PMIC system, an advanced power delivery network (PDN) is proposed to minimize the supply voltage variation and transient time using face-to-face interconnection between AP package and partitioned voltage regulators (PVRs) chip from PMIC package. The voltage variation of the InFO_PoP with PVRs system is 43% lower than that of the FC_PoP with PVRs system. Meanwhile, the InFO_PoP with PVRs system exhibits immediate transient response. The transient time of InFO_PoP with PVRs system is 54% less than that of the FC_PoP with PVRs system.

A novel 3D InFO inductor is developed to integrate with TSMC 16nm FinFET devices for high efficiency integrated voltage regulator (IVR) design. The 3D InFO inductor is designed using thick through-InFO-via (TIV) copper, where the form factor is 1.4 × 2.2 × 0.15 mm 3 . It performs 2.14 nH inductance at 140 MHz and 3.2 mΩ resistance at DC. The resistance of power delivery network (PDN) between inductor and load is 1.1 mu. The InFO technology provides the low resistance 3D inductor and PDN concurrently for the IVR system design to achieve a peak power efficiency of 93%.