Interconnect

A novel approach of copper CMP stop layer using uncured extreme low-K was demonstrated to improve the within-wafer Rs uniformity on Cu/extra low-k (XLK) interconnect. This CMP stop layer could be converted into a low dielectric constant film by removing porogen with post CMP treatment, hence its impact on overall’s film capacitance is minimized.

This research focus on low radical plasma etch (LRPE) process and its impact on highly porous dielectric material (extreme-low-k, ELK, k=2.4). We demonstrate a dual damascene (DD) process flow without k degration by low radical and pore sealing plasma etch. Comparing to tranditional DD etching process, 12% resistance-capacitance (RC) improvement, 15% via resistance reduction and a factor of 3 inter-metal-dielectric (IMD) time dependent dielectic breakdown (TDDB) improvement can be achieved by the proposed approach.

This study reports the effect of different barrier on Cu interconnect performance. A thin “enhancement” layer of Ru or Co film is deposited between a PVD Ta(N) liner barrier and a Cu seed layer to improve copper to barrier adhesion and copper gap fill. With the enhancement layer of either Ru or Co, no void is found in dual damascene structure with very thin seed. The electrical performance is improved with more than two times of EM lifetime is observed. The seedless electroplating on the enhancement layers capability will maximize the gap fill window.

Challenges of various low effective-K approaches, including homogeneous low-K and air-gap, for next generation Cu/low-K interconnect will be presented. For homogeneous low-K approach, top issues and possible solutions for K damage, package, and CMP peeling & planarization due to introduction of fragile lower k (KLt2.4) insulator will be focused. For air-gap, various types of air-gaps will be reviewed from the points of cost, layout/designer, and new processes involved.

Various integration approaches, including homogeneous porous Low-k and air gaps, for low-capacitance solution were investigated for 22 nm Cu interconnect technology and beyond. For homogeneous Low-k approach, K=2.0 Low-k material is successfully integrated with Cu. Up to 15% line to line capacitance reduction compared with LK-1 (K= 2.5) was demonstrated by a damage-less etching and CMP process. For air gap approach, a cost-effective and Selective air gaps formation process was developed. Air gaps are selectively formed only at narrow spacing between conduction lines without additional processes.

The diffusion coefficient of Cu in (Ti, Zr)N was measured by X-ray diffraction (XRD) and four-point probe (FPP) analyses after annealing Cu/(Ti, Zr)N/Si multilayered samples in the temperature range of Cu diffusion in (Ti, Zr)N had components from both the grain boundaries and the lattice based on diffusional analysis. This study suggests that for the measurement of the diffusion coefficient of Cu, FPP analysis is more precise and sensitive than XRD analysis. Additionally, (Ti, Zr)N has better Cu diffusion barrier properties than those of TaN and TiN. © 2004 The Electrochemical Society. All rights reserved.

We demonstrate a superpolishing electrolyte, which consists of acid additives in conventional Cu polishing electrolytes for efficiently planarizing Cu damascene features. The significant additive concentration gradient in features, resulting in a selective Cu dissolution rate within features, is explored as a major mechanism that yields such electrolytes with high planarization efficiency. Moreover, another additive, polyethylene glycol as a suppressor, is also employed to reduce oxygen bubbling on polished films. Consequently, a smooth surface with a complete step height elimination is obtained in a 70 μm trench after electropolishing.

In this work, a selective CoWP metal cap was employed after Cu CMP process for replacing conventional dielectric cap layer platform. A 5% reduction in RC delay was demonstrated for this new approach. The CoWP cap layer improves the interface between Cu and dielectric layer which reduces the Cu surface migration. EM for both via and trench shows more than 10X improvement. With optimized thickness and deposited process, 100% yield of line to line leakages, via chain Rc, and metal line Rs can be achieved. A semi-quantitative model was employed to determine surface migration dominating EM failure.

Eight level Cu/CVD low-k (k<2.5) + one top level Cu/USG 90 nm multilevel interconnection with 0.12/0.12 /spl mu/m for line width/space and 0.13 /spl mu/m for via has been demonstrated for the first time using 193 nm lithography with OPC developed for TSMC 200 mm/300 mm technologies. The 8-level Cu/CVD low-k dual damascenes were constructed by nitrogen-free dielectric layers without middle trench etch stop to achieve keff=2.6. No film delamination was found by film and CMP optimization. Electrical results showed that excellent and thermally stable metal-line Rs and via-chain Rc yields from iso or dense Cu areas and 1M via chains were obtained.

As the device dimension continues to shrink, the need for a thinner barrier for copper has risen in order to meet the requirements for future device performance. The conventional barrier process by physical vapor deposition (PVD) has the limitation to achieve conformal step coverage across the dual damascene structure , and therefore would face a bottleneck when the thickness reduction is required. In this work, the atomic layer deposition (ALD) technique is applied for the TaN barrier process of a 90 nm generation copper dual damascene integration with low-k dielectrics of k=3.0. The ALD technique could not only provide a conformal step coverage on both trenches and vias, it could also allows reasonable thickness control for thickness of the order of 10 /spl Aring/. The integration results show that ALD TaN has promising electrical performance on sheet resistance, via resistance, and line-to-line leakage, and it also has superior reliability performance on electromigration, stress migration, and bias temperature test as compared with conventional PVD TaN.