On-chip Interconnect

On-chip interconnect today is based on copper/low-k wiring – in today’s chips, there can be more than 100 km of copper wires.

TSMC’s leading edge technologies use a novel copper gap-fill solution to enable the fabrication of smaller conductor lines. Newly-developed materials and processes allow significant reduction in line and via resistance to improve chip performance. A comprehensive suite of innovations on integration scheme, low-k material, and low-k process with selective deposition further enhance both performance (through capacitance reduction) and reliability. Beyond copper interconnect, explorations of single metallic elements, binary and ternary alloys, and 2D materials for future interconnect materials are underway both within TSMC and with our academic partners.

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11-20 of 24
  • A new enhancement layer to improve copper interconnect performance

    This study reports the effect of different barrier on Cu interconnect performance. A thin “enhancement” layer of Ru or Co film is deposited between a PVD Ta(N) liner barrier and a Cu seed layer to improve copper to barrier adhesion and copper gap fill. With the enhancement layer of either Ru or Co, no void is found in dual damascene structure with very thin seed. The electrical performance is improved with more than two times of EM lifetime is observed. The seedless electroplating on the enhancement layers capability will maximize the gap fill window.
  • Challenges of Low Effective-K approaches for future Cu interconnect

    Challenges of various low effective-K approaches, including homogeneous low-K and air-gap, for next generation Cu/low-K interconnect will be presented. For homogeneous low-K approach, top issues and possible solutions for K damage, package, and CMP peeling & planarization due to introduction of fragile lower k (KLt2.4) insulator will be focused. For air-gap, various types of air-gaps will be reviewed from the points of cost, layout/designer, and new processes involved.
  • Low capacitance approaches for 22nm generation Cu interconnect

    Various integration approaches, including homogeneous porous Low-k and air gaps, for low-capacitance solution were investigated for 22 nm Cu interconnect technology and beyond. For homogeneous Low-k approach, K=2.0 Low-k material is successfully integrated with Cu. Up to 15% line to line capacitance reduction compared with LK-1 (K= 2.5) was demonstrated by a damage-less etching and CMP process. For air gap approach, a cost-effective and Selective air gaps formation process was developed. Air gaps are selectively formed only at narrow spacing between conduction lines without additional processes.
  • Diffusion of Copper in Titanium Zirconium Nitride Thin Films

    The diffusion coefficient of Cu in (Ti, Zr)N was measured by X-ray diffraction (XRD) and four-point probe (FPP) analyses after annealing Cu/(Ti, Zr)N/Si multilayered samples in the temperature range of Cu diffusion in (Ti, Zr)N had components from both the grain boundaries and the lattice based on diffusional analysis. This study suggests that for the measurement of the diffusion coefficient of Cu, FPP analysis is more precise and sensitive than XRD analysis. Additionally, (Ti, Zr)N has better Cu diffusion barrier properties than those of TaN and TiN. © 2004 The Electrochemical Society. All rights reserved.
  • Superpolishing for Planarizing Copper Damascene Interconnects

    We demonstrate a superpolishing electrolyte, which consists of acid additives in conventional Cu polishing electrolytes for efficiently planarizing Cu damascene features. The significant additive concentration gradient in features, resulting in a selective Cu dissolution rate within features, is explored as a major mechanism that yields such electrolytes with high planarization efficiency. Moreover, another additive, polyethylene glycol as a suppressor, is also employed to reduce oxygen bubbling on polished films. Consequently, a smooth surface with a complete step height elimination is obtained in a 70 μm trench after electropolishing.
  • High performance/reliability Cu interconnect with selective CoWP cap

    In this work, a selective CoWP metal cap was employed after Cu CMP process for replacing conventional dielectric cap layer platform. A 5% reduction in RC delay was demonstrated for this new approach. The CoWP cap layer improves the interface between Cu and dielectric layer which reduces the Cu surface migration. EM for both via and trench shows more than 10X improvement. With optimized thickness and deposited process, 100% yield of line to line leakages, via chain Rc, and metal line Rs can be achieved. A semi-quantitative model was employed to determine surface migration dominating EM failure.
  • 90 nm generation Cu/CVD low-k (k < 2.5) interconnect technology

    Eight level Cu/CVD low-k (k<2.5) + one top level Cu/USG 90 nm multilevel interconnection with 0.12/0.12 /spl mu/m for line width/space and 0.13 /spl mu/m for via has been demonstrated for the first time using 193 nm lithography with OPC developed for TSMC 200 mm/300 mm technologies. The 8-level Cu/CVD low-k dual damascenes were constructed by nitrogen-free dielectric layers without middle trench etch stop to achieve keff=2.6. No film delamination was found by film and CMP optimization. Electrical results showed that excellent and thermally stable metal-line Rs and via-chain Rc yields from iso or dense Cu areas and 1M via chains were obtained.
  • A 90 nm generation copper dual damascene technology with ALD TaN barrier

    As the device dimension continues to shrink, the need for a thinner barrier for copper has risen in order to meet the requirements for future device performance. The conventional barrier process by physical vapor deposition (PVD) has the limitation to achieve conformal step coverage across the dual damascene structure , and therefore would face a bottleneck when the thickness reduction is required. In this work, the atomic layer deposition (ALD) technique is applied for the TaN barrier process of a 90 nm generation copper dual damascene integration with low-k dielectrics of k=3.0. The ALD technique could not only provide a conformal step coverage on both trenches and vias, it could also allows reasonable thickness control for thickness of the order of 10 /spl Aring/. The integration results show that ALD TaN has promising electrical performance on sheet resistance, via resistance, and line-to-line leakage, and it also has superior reliability performance on electromigration, stress migration, and bias temperature test as compared with conventional PVD TaN.
  • CVD barriers for Cu with nanoporous ultra low-k: integration and reliability

    The drive for greater integrated circuit performance has led to the need for faster interconnect systems, the development of porous ultra low-k dielectrics and thin CVD barriers. The porous structure and lower modulus of low-k dielectrics has made integration a greater challenge. In this paper, we report on an initial feasibility study on of a new spin-on nanoporous low-k dielectric with a CVD TiN(Si) barrier, for Cu dual damascene integration.
  • CMP-free and CMP-less approaches for multilevel Cu/low-k BEOL integration

    A CMP-free process by electropolishing (EP) the planar contact plating (CP) Cu film and TaN dry etching which eliminate the stress induced peeling during CMP was demonstrated. Nanometer smoothness and a highly <111> texture of Cu can be achieved by optimizing the EP process. A 4-level Cu/low-k interconnect with CMP-less process was demonstrated with excellent yield. This process improves the throughput on ECP and CMP by two and has less dishing.
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