Interconnect

5G and AI technologies are widely applied to highly connected world across cloud, network and edge applications. The compute and bandwidth of high performance computing (HPC) systems such as supercomputer, data center and high-end servers are constantly upgraded to fulfill the ever-increasing challenge from data analytic workload on massive and complicated data. As such, the thermal dissipation issue becomes more of a concern when advanced technology node logic processor operates at high frequency, in particular co-packages with high bandwidth memory (HBM). In this study, we present an industry first advanced liquid cooling technology for HPC on a CoWoS (Chip on Wafer on Substrate) with thermal design power (TDP) up to 2KW. The measurement results show the junction-to-ambient thermal resistance θJA is about 0.064 (°C/W) for lidded liquid cooling with thermal interface material (TIM) and 0.055 (°C/W) for direct liquid cooling at a flow rate of 40 ml/s. A finite element analysis model is further applied to find out the influence of key parameters on the heat dissipation performance.

In order to ensure good performance and long-term reliability of fan-out package, the interfacial strength of Underfill (UF) and polymer (PM) lamination plays an important role because of physical strength and electrical requirement. Accordingly, the present study presents a combined experimental and finite element modeling approach for quantitatively determining the interfacial adhesive strength of UF-PM structures. In the proposed approach, four points bending (FPB) testing is used to evaluate the adhesion strength between UF-PM. The test results are used to determine the critical strain energy release rate (Gc) at the UF-PM interface. The experimental results are then taken as a reference for finite element (FE) simulations. The virtual crack closure technique (VCCT) in FE model is introduced here for risk assessment such as delamination or crack risk at the interface of UF-PM. In general, the results confirm that the proposed predictive modeling approach provides an effective means of evaluating the delamination risk in UF-PM systems. As such, it provides a convenient and cost-effective method for evaluating the new material interface of UF-PM.

One of the prominent challenges for widespread adoption of Si photonics (SiPh) technology is the availability of an integration platform that can simultaneously meet a wide range of power, performance, and cost criteria in different applications. As a result, there is a diversity of Si photonics integrated solutions proposed or demonstrated, but none is considered as a common solution. In this paper, we will first survey industry proposed photonic engine (PE) structures in monolithic, 2D, 2.5D, and 3D on their strengths and weaknesses. We will then propose a compact and universal PE structure- COUPE (COmpact Universal Photonic Engine) that could consolidate different requirements onto the same integration platform. COUPE has the EIC-PIC integration with the electrical interface designed to minimize the EIC-PIC coupling loss. Compared with industry proposed PE technology, COUPE can provide low insertion loss for both grating coupler (GC) and edge coupler (EC). For either GC or EC, the COUPE is a solid structure without cavities or mechanically weak parts, thus enabling low insertion loss without contamination or mechanical concerns. COUPE also has the flexibility to be integrated easily with host ASIC to form a co-package structure. The COUPE integration scheme can meet the most demanding system requirements and pave the way for silicon photonics based wafer level system integration (WLSI) for high performance computing (HPC) applications.

One of the prominent challenges for widespread adoption of Si photonics (SiPh) technology is the availability of an integration platform that can simultaneously meet a wide range of power, performance, and cost criteria in different applications. As a result, there is a diversity of Si photonics integrated solutions proposed or demonstrated, but none is considered as a common solution. In this paper, we will first survey industry proposed photonic engine (PE) structures in monolithic, 2D, 2.5D, and 3D on their strengths and weaknesses. We will then propose a compact and universal PE structure- COUPE (COmpact Universal Photonic Engine) that could consolidate different requirements onto the same integration platform. COUPE has the EIC-PIC integration with the electrical interface designed to minimize the EIC-PIC coupling loss. Compared with industry proposed PE technology, COUPE can provide low insertion loss for both grating coupler (GC) and edge coupler (EC). For either GC or EC, the COUPE is a solid structure without cavities or mechanically weak parts, thus enabling low insertion loss without contamination or mechanical concerns. COUPE also has the flexibility to be integrated easily with host ASIC to form a co-package structure. The COUPE integration scheme can meet the most demanding system requirements and pave the way for silicon photonics based wafer level system integration (WLSI) for high performance computing (HPC) applications.

The continuous pursuit of higher compute power with insatiable data bandwidth to meet relentless AI system demands from cloud computing, data centers, enterprise servers, supercomputers, network system and edge computing, has urged new system integration solutions with larger footprint, denser 3D interconnect, close proximity 3D inter-chip integration and new memory system. Recent years, chiplets integration has prevailed in high performance computing (HPC) for cost and performance consideration. For HPC networking applications, the network switch capacity has increased from 6.4 Tb/sec to 25.6 Tb/sec to meet ever-increasing big data growth in cloud and data center for AI training, deep learning, and inferencing. Single advanced node SoC switch chip solution no longer meets the switch capacity growing demand due to cost and performance consideration. To resolve this issue, we have developed InFO_oS (InFO on Substrate) technology featuring multiple tiers of high density 2/2μm RDL line width/space to integrate multiple advanced node switch chiplets for cost and performance. In this paper, we present the industry’s first 2.5x reticle size of fan-out (2100 mm2) with 110x110 mm2 substrate integration. The 2.5x test vehicle integrates 10 chiplets, 2 logic and 8 IO dies, through 5 layers of RDLs interconnection. Various stacking-via has been evaluated to provide more design flexibility and area miniaturization. InFO_oS is integrated on a wafer base, so it can fully leverage the tools, materials, process know-how, and manufacturing capacity of InFO technology platform for design flexibility, yield and fast time to market. Through process optimization, a promising high electrical yield has been achieved with D2D connection >95%. Process challenges and the results of component-level reliability (uHAST/TC/HTS) will be also addressed.

Organic interposer (CoWoS®-R) is one of the most promising heterogeneous integration platform solutions for high-speed and artificial intelligence applications. Components such as chiplets, high-bandwidth memory, and passives can be integrated into an organic interposer with excellent yield and reliability. This paper presents reliability results for advanced organic interposer packages. Multiple redistribution layers (RDLs) form an effective stress buffer for reducing the stress induced in the C4 joint and its underfill from the mismatch between the top dies and substrate. Four RDL lines with a minimum line width/spacing of 2/2 μm exhibited excellent robustness, ensuring the long functional lives of high performance computing products. We successfully demonstrated the outstanding fatigue performance of the C4 joint reliability. Various large packages passed stringent reliability tests, specifically TCC (−65°C to 150°C) up to 1300 cycles for heterogeneous integration package and TCG (−40°C to 125°C) up to 2500 cycles for chiplet integration package. The results of the sanity cross-sectional check indicate no interfacial delamination or crack. In addition, an in-depth analysis conducted using finite-element modeling revealed that the packages had superior reliability performance compared with a large monolithic flip-chip package.

Along with HPC electrical performance evolution, larger size and more layers ABF substrate play one of key roles to be the succeeded, however as it transpired recently ABF substrate become the major bottleneck by yield or transmission loss control to cause computing component shortage. An Innovative SoIS (System on Integrated Substrate) technology is proposed to satisfy higher performance applications cost effectively. SoIS technology leverages wafer process and new materials. This innovative integrated substrate presented significantly higher yield than conventional substrate solutions on the TVs with 91x91mm2 substrate size. The electrical TV showed that the insertion loss is 25% lower than that of the most updated GL102 organic substrate at 28GHz for 112Gbps SerDes application. The mechanical/electrical TV has passed package-level reliability tests including MSL4+ (TCG2000, uHAST360) and HTS1500. Microstructure sanity check after reliability torture tests was also proven to pass quality & reliability criteria. Furthermore, by leveraging wafer fab process, SoIS also could provide powerful yet flexible combinations in interconnect and dielectric layer with more aggressive design rule than conventional organic substrate did. Especially, for high bandwidth routing density applications, SoIS can enhance 2~5 times rout-ability than conventional organic substrates to save not just layer counts but also keep the same impedance matching performance without adding extra cost, which have been proven by simulation and Si data successfully.

Chip-on-Wafer-on-Substrate (CoWoS-S) is a TSV-based multi-chip integration technology that has been in production for close to 10 years. It is widely used in high performance computing (HPC) and artificial intelligence (AI) accelerator area due to its flexibility to accommodate multiple chips of SoC, chiplet, and 3D stacks such as high bandwidth memory (HBM). The interposer size increases steadily over the past few years, from one full reticle size (~830 mm2) to two reticle size (~1700 mm2). The growth of interposer size offers more integration power to accommodate more active silicon in a package to satisfy the HPC/AI needs. In this paper, we report the new 5th generation CoWoS-S (CoWoS-S5) based on a Si interposer at three full reticle size (~2500 mm2) by a novel mask stitching approach. This will accommodate simultaneously multiple logic chips at a total area of 1200 mm2 (with chiplets) together with eight HBM stacks. In addition to dimensional increase in the Si interposer, new features are incorporated in the system to further enhance the electrical and thermal performances of CoWoS-S5 compared with the previous CoWoS-S portfolio. These include a 2nd generation integrated capacitor (iCap) for further enhanced power integrity, 5 layers of sub-micron Cu interconnect with lower sheet resistance to satisfy high speed die to die interconnect, new TSV structure interposer for both return and insertion loss reduction with good package reliability, and a higher thermal conductivity thermal interface material (TIM) to achieve a lower thermal resistance. Component level reliability with excellent electrical and physical results are also discussed.

This work shows a system for power delivery network (PDN) impedance measurements (PIM), targeting high-performance computing (HPC) applications. A delay-line based "TRIG-after-SAMP" approach relaxes timing margins and eliminates high-speed clock sources. On-chip DUTs, with two bonding schemes and a programmable de-coupling capacitor array, are demonstrated using 7nm FinFET technology. Measurement results show that this system achieves a sampling bandwidth of 27 GHz, an accuracy of 1 mV, and a core area of 0.028 mm2.

An array-based test-vehicle for tracking bit-error-rate (BER) degradation of signal interconnects subject to DC electromigration (EM) stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. BER measurement results from four individual interconnect paths are presented and analyzed.