Interconnect

The drive for greater integrated circuit performance has led to the need for faster interconnect systems, the development of porous ultra low-k dielectrics and thin CVD barriers. The porous structure and lower modulus of low-k dielectrics has made integration a greater challenge. In this paper, we report on an initial feasibility study on of a new spin-on nanoporous low-k dielectric with a CVD TiN(Si) barrier, for Cu dual damascene integration.

A CMP-free process by electropolishing (EP) the planar contact plating (CP) Cu film and TaN dry etching which eliminate the stress induced peeling during CMP was demonstrated. Nanometer smoothness and a highly <111> texture of Cu can be achieved by optimizing the EP process. A 4-level Cu/low-k interconnect with CMP-less process was demonstrated with excellent yield. This process improves the throughput on ECP and CMP by two and has less dishing.

Electromigration (EM) characteristics were evaluated for multilevel copper test structures embedded in a CVD SiOC low k inter-metal dielectric. After electromigration stress testing, Cu extrusion along the interface between SiOC and the SiN dielectric diffusion barrier was revealed as the primary cause of EM failure. No evidence of cracking or mechanical weak points was observed in the bulk SiOC film; thus improved EM lifetime is expected from enhancement in the adhesion strength of SiN to SiOC. The calculated EM activation energies for 0.35 /spl mu/m via chains and 0.5 /spl mu/m via chains are 0.82 eV and 0.93 eV, respectively. The current density exponent (n) was measured to be about 1, which is consistent with the void growth mechanism in Cu. The critical length was found to decrease with increasing current density, and the j/spl middot/L/sub c/ product was determined to be approximately 7500 A/cm.

The self-annealing and the surface reflectivity of Cu films prepared by electrochemical deposition (ECD) are obtained for the DC and pulse reverse processes. They show different behaviors for these two processes, and their behaviors can be well correlated with the grain size of the films. The mechanism of gap fill is discussed according to the surface profile after gap fill for these two processes. It is proposed that the gap filling is mainly controlled by the additive diffusion for the DC process, while it is mainly controlled by the additive adsorption for the pulse reverse process.

The electromigration (EM) and bias temperature stress (BTS) performances of Cu metallization in dual damascene structure were examined. The experimental results show that Cu has more than one order of magnitude EM lifetime relative to Al alloy. The activation energy of electromigration of Cu trench is 0.9 eV. The failure sites of Cu dual damascene process after EM stress testing are mainly in the bottom of cathode site's vias. Via electromigration can be improved up to one order magnitude by optimizing several processes such as PR stripping, pad structure, etc. BTS study results indicate that the activation energy of Cu ion drift leakage is around 1.1 to 1.4 eV. The interface of capping SiN and SiO/sub 2/ was found to be the major copper diffusion path. Lifetime extrapolated from the empirical data indicates that the device can sustain longer than 1000 years under normal operation condition.

Ta-based Cu diffusion barrier properties were widely studied. This work demonstrates that grain boundary diffusivity of Cu diffusion in various TaN/sub x/ (x=0/spl sim/0.62) thin films can be extracted from the copper concentration profile, based on the Whipple analysis of grain boundary diffusion, after annealing the samples at fixed temperatures between 200 and 500/spl deg/C. We used the grain boundary diffusivity to predict the penetration depth (2/spl radic/Dt) of Cu in Ta and TaN/sub x/ films at fixed temperatures 250 and 400/spl deg/C. Cu/TaN/sub x/(45 A)/N/sup +/P junction diode leakage, SIMS and XSEM analysis results indicated that the Whipple model correlates well with experimental results.