Events

Future electronic systems will continue to rely on, and increasingly benefit from, the advances in semiconductor technology as they have had for more than five decades. Since its inception, the semiconductor industry has used a physical dimension (minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. Density is what drives the benefits of new device technologies for computation – the primary application driver for semiconductors. Going forward, we will use a three-prong metric that consists of logic density (DL), memory bit density (DM), and interconnect density between logic and memory (DC) as a means to capture how advances in semiconductor device technologies enable system level benefits. Because DL and DM will increase at a slower rate than the historical trends, technologies that address the connectivity will become primary drivers for technology advancement. This trend is already visible in HPC products that progressively leverage more capable packaging technologies including 3D chip stacking. Indeed, vertical interconnect density associated with advanced packaging featured about three orders of magnitude improvement in the last decade alone. Scaling vertical interconnect pitch to sub-100 nm would enable another four orders of magnitude improvement. As such, there is plenty of room for system-level advances based on 3D ICs. The distinction between on-die connectivity (vias and on-chip interconnect wires) and off-chip connectivity (e.g. TSVs and micro-bumps) will become increasingly blurred. Wafer-level monolithic integration technologies and packaging technologies will smoothly blend into one another. New design tools that optimally perform system partitioning will become indispensable.

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Packaging technology used to play mainly a protection role in the supply chain for IC, which follows the path of Moore’s Law with system-on-chip. When chip scaling becomes more challenging and, at the same time, we want to integrate more functions such as memory, sensors and passives, etc. for new applications such as AI and 5G, etc, innovative heterogeneous integration technologies are proposed for system-on-package to provide critical PPA values of the micro-systems. We are making far-reaching changes, which initiate an exciting new semiconductor era and create a new industry landscape.

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Internet of things and artificial intelligence demand further performance improvements in integrated circuit systems. One ongoing effort is to continue the transistor scaling with either new device architectures or adopting new materials with superior gate controllability. Another attractive approach is to construct three-dimensional integrated circuits (3D ICs) with monolithic integration; for example, adding sensor functionalities, or constructing upper-layer logic circuits or memory devices on CMOS Si wafers. The research on materials and processes compatible with the backend-of-line (BOEL) fabrication temperature (< 400 oC), is urgently needed. In this presentation, I like to discuss on few potential components useful for achieving monolithic 3D ICs including 2D layered materials such as transition metal dichalcogenide based semiconductors, hexagonal boron nitride (hBN) insulators, and 1D semiconducting carbon nanotubes. The proof-of-concept monolithic integration of carbon nanotube transistors on our 28 nm CMOS technology wafers has also been demonstrated.

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The gate controllability becomes weaker when a conventional silicon field-effect transistor (FET) shrinks in lateral dimension owing to source-drain tunneling. Hence the transistor body thickness needs to be reduced to ensure efficient electrostatic control. New materials with perfect surfaces are therefore needed and 2D semiconducting materials offer a chance to continue the scaling. In this presentation, we present an analysis on the foreseeable challenges including 2D materials selection, achieving high mobility, formation of high-k gate metal stacks, source/drain metal-2D contact, and large-area or scalable growth of 2D layered materials for devices applications. Possible approaches to address the above mentioned issues shall be presented. Recent progresses of the efforts moving towards electronics based on 2D materials will be discussed.

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