Semiconducting graphene nanoribbons via anisotropic CVD
Seminars @ TSMC
Feb 27 2019
Medical Electronic Devices: Monitoring Health and Tracking Disease Progression
Seminars @ TSMC
Feb 25 2019
Progress and Challenges for Engineering Superconducting Qubits
Seminars @ TSMC
Jan 25 2019
Silicon-based quantum computing: The path from the laboratory to industrial manufacture
Seminars @ TSMC
Jan 24 2019
Micro-magnet Techniques for Implementing Spin-based Quantum Computing with Quantum Dots
Seminars @ TSMC
Jan 23 2019
TSMC-NTU Research Symposium
Workshops @ TSMC
Jan 18, 2019
The fourth International Conference on 2D Materials and Technologies (ICON-2DMAT 2018)
Internet of things and artificial intelligence demand further transistor performance improvements and device size scaling. In a conventional planar silicon field-effect transistor (FET), the gate controllability becomes weaker when its lateral dimension scales. Hence the transistor body thickness needs to be reduced to ensure efficient electrostatic control from the gate. When the silicon thickness reduces to a few nanometers, the fast mobility decay owing to the scatterings from imperfect silicon surfaces retards the further scaling. New materials with perfect surfaces are therefore needed and 2D semiconducting materials offer a great chance to continue the scaling. Silicon transistor evolution (road map) shall be discussed first. Many challenges are ahead for adopting 2D semiconductors as FET channel materials, including (1) selection of 2D materials, (2) reduction of contact resistance, (3) growth of wafer-scale and single-crystalline 2D materials, and (4) Integration of 2D materials to existing microelectronic fabrication processes. In this presentation, we will share our perspectives on these challenges and possible approaches.
Invited Talks
Dec 10 - 13, 2018
The 10th annual Recent Progress in Graphene and Two-dimensional Materials Research Conference (RPGR2018)
Internet of things and artificial intelligence demand further transistor performance improvements and device size scaling. In a conventional planar silicon field-effect transistor (FET), the gate controllability becomes weaker when its lateral dimension scales. Hence the transistor body thickness needs to be reduced to ensure efficient electrostatic control from the gate. When the silicon thickness reduces to a few nanometers, the fast mobility decay owing to the scatterings from imperfect silicon surfaces retards the further scaling. New materials with perfect surfaces are therefore needed and 2D semiconducting materials offer a chance to continue the scaling. Silicon transistor evolution shall be discussed first. Many challenges are ahead for adopting 2D semiconductors as FET channel materials, including (1) selection of 2D materials, (2) reduction of contact resistance, (3) growth of wafer-scale and single-crystalline 2D materials, and (4) Integration of 2D materials to existing microelectronic fabrication processes. In this presentation, we will discuss on these challenges and possible approaches.
