Events

The gate controllability becomes weaker when a conventional silicon field-effect transistor (FET) shrinks in lateral dimension owing to source-drain tunneling. Hence the transistor body thickness needs to be reduced to ensure efficient electrostatic control. New materials with perfect surfaces are therefore needed and 2D semiconducting materials offer a chance to continue the scaling. In this presentation, we present an analysis on the foreseeable challenges including 2D materials selection, achieving high mobility, formation of high-k gate metal stacks, source/drain metal-2D contact, and large-area or scalable growth of 2D layered materials for devices applications. Possible approaches to address the above mentioned issues shall be presented. Recent progresses of the efforts moving towards electronics based on 2D materials will be discussed.

SEE MORE