Ultra-low leakage 0.16 μm CMOS for low-standby power applications
In this work, low leakage 0.16 /spl mu/m CMOS devices (T/sub ox/=32 /spl Aring/) with various off-state leakage currents (I/sub off/) were fabricated and studied for low standby power applications. Specifically two different device designs are introduced here. One design code named LP is targeted for worst-case I/sub off/<3 pA//spl mu/m. Another design, code named ULP (ultra low-power), is targeted for even stringent worst-case I/sub off/<0.3 pA//spl mu/m. This work demonstrates n/pMOSFETs with 575/230 and 370/165 /spl mu/A//spl mu/m drive currents @1.8 V for LP and ULP specifications respectively. Cobalt salicide process was also optimized for low junction leakage (<100 pA/cm). The 0.16 /spl mu/m process capability for ultra-low power applications was demonstrated using a CMOS 4 Mbit SRAM with measured minimum standby current <0.2 /spl mu/A at the single power supply voltage V/sub CC/=3 V.
Logic
Logic
TSMC has been at the forefront of advanced CMOS logic technologies for which dense transistors are one of the two essential building blocks, the other being dense interconnect stacks. The intrinsic computing capability of a given logic technology is directly related to the number of interconnected transistors and their switching speed under representative loads originating from both the transistor or gates being driven and the related interconnect resistive and capacitive circuit loads.
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