Power Saving and Noise Reduction of 28nm CMOS RF SystemIntegration Using Integrated Fan-Out Wafer Level Packaging (InFO-WLP) TechnologyAn integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of -53 dB. With the 3DSI, the RF system in the InFO technology results in power saving by 58% and noise reduction by 80% in LNA and VCO, respectively, compared with those in RF SoC system. The InFO technology provides a novel solution for RF system integration.
New System-in-Package (SiP) Integration technologiesNew System-in-Package (SiP) with innovative Wafer-Level-System-Integration (WLSI) technologies that leverage foundry core competence on wafer processes have been demonstrated. The WLSI technologies include Chipon-Wafer-on-Substrate (CoWoSTM) 3DIC and interposer, Integrated Fan-Out (InFO) and Chip-Scale Wafer-LevelPackaging. Wide application portfolio from very low I/O pin-count, low-cost devices, to medium, high and ultra-high pin-count are realized. Chip-partition followed by flexible powerful integration of single-chip or multi-chips, advanced or matured Si, logic and memory, SoC and sensor/MEMS. System values include low profile, low power, high bandwidth along with competitive cost can be readily achieved. With the chip-partition, we can sustain Moore’s law longer.
A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integrationA reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (V cc ) of 1.8V, and a leakage current (I LK ) below 1 fA/μm 2 under +/-2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/μm 2 , respectively, with their corresponding I LK below 0.48, 0.19 and 0.09 fAmp/μm 2 . Process reliability related defect density (D 0 ) of the interposer HK-MiM is as low as 0.095% cm -2 as judged by a 10 years lifetime breakdown voltage (V bd ) criterion at V cc =3.2V. This low D 0 ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm 2 within the Si interposer. Moreover, the V bd tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., I LK & V bd tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.
Wafer Level System Integration for SiPA family of novel wafer-level-system-integration technologies (WLSI) was proposed. This paper reviews WLSI feasibility work first. Further results on the reliability, the compatibility of the integration with both more advanced node Logic and DRAM devices, and the higher-level system integration of the WLSI technologies are then presented. Foundry has established a comprehensive system integration technology portfolio in wafer form to fulfill the needs from mobile to cloud computing for the future growth of the Si-based nano-electronics industry.
Reliability Evaluation of a CoWoS-enabled 3D IC PackageTSV (Through Silicon Via)-based interposer has been proposed as a multi-die package solution to meet the rapidly increasing demand in inter-component (e.g. CPU, GPU and DRAM) communication bandwidth in an electronic system. he stacked-silicon die package configuration may give rise to package reliability concerns not observed in conventional monolithic flip-chip packages. 3D finite element method (FEM) was used to study the thermo-mechanical response of the interposer-based package during thermal cycle reliability stressing. Fatigue failures of the C4 and BGA joints are the two primary reliability focuses in the present study. Experimental data collected on the CoWoSTM-enabled test vehicles were used to validate the FEM models. Parametric study of key package material and geometric parameters was performed to analyze their effects on C4 bump thermal cycle reliability. Package materials of interest include UF (underfill), lid and substrate, and the geometric parameters include lid thickness and C4 bump scheme. The results showed that the CoWoS package using AlSiC lid has better C4 bump life than the CoWoS package using Cu lid, and when the Tg of the underfill of C4 bump is higher, the C4 bump has better reliability. Furthermore, 3D thermomechanical and reliability study of BGA balls is presented for organic and ceramic substrates. Several DOEs have been constructed for ceramic substrate to increase BGA reliability by optimizing C4 underfill material and package design. The effect of board layer count and design is detailed. Finally reliability of BGA balls, C4 and micro-bumps are compared for a part that is mounted on a PCB board.
Array Antenna Integrated Fan-out Wafer Level Packaging (InFO-WLP) for Millimeter Wave System ApplicationsArray antenna integrated with RF chip using InFO-WLP technology is proposed for millimeter wave system applications. Aperture-coupled patch antenna is designed on the fan-out molding compound (MC). The performance of single-element antenna is evaluated first and proved to have 5 dBi of gain. Meanwhile, the interconnect from chip to antenna feeding line is demonstrated to only have 0.7 dB loss, which can save 19 % PA output power compared with that of flip-chip package. Finally, the system performance of 4 × 4 antenna array integrated with RF chip on the InFO structure shows 14.7 dBi of array gain in a small form factor of 10 × 10 × 0.5 mm 3 .
Innovative Wafer-based Interconnect Enabling System Integration and Semiconductor Paradigm ShiftsIn semiconductor world, there is a new paradigm shift from chip-scaling to system-scaling to meet the ever-increasing electronic system demands for performance and functionality, and for reduction of system form factor, power and cost. This shift is also triggered by the fast increasing challenges for industry to sustain Moore's Law. System scaling needs advanced package technologies. Conventionally, package technologies use different tool sets and different materials from those used in wafer fab. Innovative wafer-based technology is proposed here to fabricate advanced packaging that, in turn, enables the system scaling - a new paradigm shift. Another new paradigm shift enabled here is that the advanced packaging shifts from conventional packaging to the innovative wafer-based technology. The innovations cover three major system scaling architecture/technologies: wafer-level-packaging (fan-in and fan-out), through-Si-via (3DIC and interposer) and ultra-thin package-on-package (PoP) for both high performance and mobile devices. We also re-invent microelectronics, continue delivering more advanced electronic systems, and help to sustain Moore's Law.
High-Performance Inductors for Integrated Fan-Out Wafer Level Packaging (InFO-WLP)Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art quality factor (Q) = 64 in 2.4GHz inductor has been demonstrated for RF systems. For the first time, radio frequency (RF) circuits with InFO-WLP have been fabricated to illustrate how the high Q inductor can be used to dramatically improve performance and power consumption concurrently.
Manufacturability Optimization and Design Validation Studies for FPGA-Based, 3D Integrated CircuitsHeterogeneous integration of integrated circuits offers an opportunity to create new functionality with tradeoffs between cost, performance, and alternative monolithic integration complexity. We present a study of heterogeneous integration using a large, field programmable gate array (FPGA) research and development vehicle to assess the capabilities of 3D silicon interposer technology. This study includes integration on a silicon interposer of a monolithic high-performance FPGA product with a companion test chip, manufacturing flow optimization for yield and reliability, design optimization, and characterization studies. High yield and reliability metrics were achieved through stress management, robust design, and manufacturing flow optimizations. Characterization results show minimal performance impact due to through silicon via (TSV) to 10Gbps transceivers and potential improvement in performance by integrating metal-insulator-metal (MIM) capacitor on the silicon interposer. Co-design implications for 3D product integration of large, high performance FPGA's with companion die will be discussed.
High-Performance Integrated Fan-Out Wafer Level Packaging (InFO-WLP): Technology and System IntegrationIntegrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLP's high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.
Silicon interposer, high-density fine-pitch fan-out RDL and bumpless bond are the three pillars of chip-to-chip interconnect on innovative advanced heterogeneous integration technologies (HIT). Each interconnect technology provides the best PPACC in their own domains of AI and 5G networks, and is tightly associated with a wafer-level heterogeneous integration technology, namely CoWoS, InFO and SoIC, respectively, in HPC and mobile application systems.
TSMC’s off-chip interconnect technologies continues to advance for better PPACC:
- Silicon interposer: high interconnect density, high specific capacitance density, and large reticle size for exascale HPC/AI
- Fan-out: high interconnect density and large reticle size in fan-out for cost and performance in HPC/network AI
- SoIC: high 3D interconnect density with ultra-low bonding latency for energy efficient computing systems
Note: PPACC: Power consumption, Performance, Area (form factor), Cost, Cycle time to market