Observation of PCRAM Endurance Cycling Induced Porous GST Material
Large and Robust Charge-to-Spin Conversion in Sputtered Weyl Semimetal WTex with Structural Disorder
Topological insulators have recently shown great promise for ultralow-power spin-orbit torque (SOT) devices thanks to their large charge-to-spin conversion efficiency originating from the spin-momentum-locked surface states. Weyl semimetals, on the other hand, may be more desirable due to their spin-polarized surface as well as bulk states, robustness against magnetic and structural disorder, and higher electrical conductivity for integration in metallic magnetic tunnel junctions. Here, we report that sputtered WTex thin films exhibit local atomic and chemical structures of Weyl semimetal WTe2 and host massless Weyl fermions in the presence of structural disorder at low temperatures. Remarkably, we find superior spin Hall conductivity and charge-to-spin conversion efficiency in these sputtered WTex films compared with crystalline WTe2 flakes. Besides, the strength of unidirectional spin Hall magnetoresistance in annealed WTex/Mo/CoFeB heterostructure is up to 20 times larger than typical SOT/ferromagnet bilayers reported at room temperature. We further demonstrate room temperature field-free magnetization switching at a current density as low as 0.97 MA/cm2. These large charge-to-spin conversion properties that are robust in the presence of structural disorder and thermal annealing pave the way for industrial production of Weyl semimetals. Our results open up a new class of sputtered Weyl semimetals for memory and computing based on magnetic tunnel junctions as well as broader planar heterostructures containing SOT/ferromagnet interfaces.
Memory
Memory
Data is the most valuable resource in today’s digital economy. Currently over 2.5 quintillion (1018) bytes of data are generated daily and the pace is accelerating. More data than ever needs to be processed. Memory plays a key role in the flow of data. The gap between logic and memory is a bottle neck to system performance. To optimize the trade-off between cost and performance, a hierarchical memory system has been adopted. At the top of the hierarchy are static random access memories (SRAM) and dynamic random access memory (DRAM), both inherently volatile. SRAM is integrated right on the logic chips as cache memory to provide fastest access. DRAM is physically smaller than SRAM and consequently supports higher capacity. DRAM is generally an off-chip memory solution and ~10x slower than SRAM due to the need for constant refresh. Non-volatile memories (NVM) such as Flash are next in the hierarchy providing much higher memory capacity and density while also preserving information in the absence of power.
Recent new technologies are emerging rapidly to bring processing tasks near to or inside the memory to improve computing efficiency and enable new functionalities. Emerging NVMs use new types of materials and mechanisms to store data. They are promising for blending the memory hierarchy to boost the overall performance. Furthermore, their unique characteristics offer great potential to enable new applications (e.g. neuromorphic computing) and novel architectures (e.g. 3D integration).
TSMC’s non-volatile memory solutions include Flash, Spin-transfer torque magnetic random access memory (STT-MRAM), and resistive random access memory (RRAM). TSMC is also actively exploring phase change random access memory (PCRAM), and spin-orbit torque MRAM (SOT-MRAM) elements, as well as selector devices which are essential to support higher density cross-point array architectures.
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