Logic

The characteristics of polysilicon resistors in sub-0.25 μm CMOS ULSI applications have been studied. Based on the presented sub-0.25 μm CMOS borderless contact, both n/sup +/ and p/sup +/ polysilicon resistors with Ti- and Co-salicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate the essential parameters of polysilicon resistors including electrical delta W(/spl Delta/W), interface resistance R/sub interface/, and pure sheet resistance R/sub pure/. This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-0.25 μm CMOS technology.

This paper investigates anomalous diffusion behavior for ultra low energy implants in the extension or tip of PMOS devices. Transient enhanced diffusion (TED) is minimal at these low energies, since excess interstitials are very close to the surface. Instead, interface induced uphill diffusion is found, for the first time, to dominate during low temperature thermal cycles. The interface pile-up dynamics can be taken advantage of to produce shallower junctions and improve short channel effect control in PMOS devices. Attempts to minimize TED before spacer deposition by inclusion of extra RTA anneals are shown to be detrimental to forming boron ultra shallow junctions.

This paper describes computer simulations of various SOI MOSFETs with double and triple gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced, The proposed device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET.

We investigate the scaling limit of base oxides treated by thermally-enhanced remote plasma nitridation (TE-RPN) for ultra-thin gate dielectric formation. Under optimized RPN conditions, this work shows gate-dielectric equivalent thickness (EOT) scalability and no transconductance degradation are characteristic of processes with base oxide thickness down to 17 /spl Aring/. Thinner base oxides result in reduced EOT scalability and transconductance degradation, resulting in /spl sim/14 /spl Aring/ manufacturable EOT limit for TE-RPN gate dielectrics.

We propose a novel process whereby Antimony Assisted Arsenic Source/Drain Extension (A/sup 3/ SDE) is employed to realize a steep and retrograde indium pocket profile for sub-0.1 /spl mu/m nMOSFETs. By engineering the defect distributions in the amorphous layer created by an indium implant, this new process improves by 8% the current drive while maintaining the same I/sub off/. It reduces nMOS diode leakage by two orders of magnitude and sidewall junction capacitance near the gate by 14%. Reliability assessment of devices fabricated by the A/sup 3/ SDE process reveals significant improvement in hot carrier effects and no observable degradation of gate oxide integrity.

This paper describes a leading-edge 0.15 /spl mu/m CMOS logic foundry technology family. Advanced core devices using 20 /spl Aring/ oxides for 1.2-1.5 V operation (L/sub G min/=0.1 /spl mu/m) support high-performance CPU and graphics applications. The technology supports also low-standby power applications with 26 /spl Aring/ oxide for 1.5 V operation. Periphery circuitry for 2.5 or 3.3 V compatibility use dual 50 or 65 /spl Aring/ gate oxides respectively. AlCu with low-k (FSG) is used for the seven-level metal interconnect system with extremely tight pitch (0.39 /spl mu/m for M1 and 0.48 /spl mu/m for intermediate levels). The aggressive design rules and border-less contacts/vias render an embedded (synchronous cache) 6T SRAM cell of 3.42 /spl mu/m/sup 2/ demonstrated in a 2Mb vehicle with very high yield. The overall process reliability is also shown to meet standard industry requirements.

A leading-edge 0.13 /spl mu/m CMOS technology using 193 nm lithography and Cu/low-k interconnect is described in this paper. High performance 80 nm core devices use 17 /spl Aring/ nitrided oxide for 1.0-1.2 V operation. These devices deliver unloaded 8.5 ps gate delay @1.2 V. This technology also supports general ASIC applications with 20 /spl Aring/ oxide for 1.2-1.5 V operation and low-standby power applications with 26 /spl Aring/ for 1.5 V operation, respectively. Dual gate oxides of 50 or 65 /spl Aring/ are also supported for 2.5 V or 3.3 V I/O circuits respectively. Cu with low-k dielectric is used for the 8-layer metal interconnect system with tight pitch. The aggressive design rules and border-less contacts/vias support a high density 1P3M 2.43 /spl mu/m/sup 2/ 6T-SRAM cell without local interconnect. A suite of embedded SRAM cells (6T, 8T) with competitive density and performance optimized for different applications are also supported with memory compilers and large block macros.

This letter presents a deep submicron CMOS process that takes advantage of phosphorus transient enhanced diffusion (TED) to improve the hot carrier reliability of 3.3 V input/output transistors. Arsenic/phosphorus LDD nMOSFETs with and without TED are fabricated. The TED effects on a LDD junction profile, device substrate current and transconductance degradation are evaluated. Substantial substrate current reduction and hot carrier lifetime improvement for the input/output devices are attained due to a more graded n/sup -/ LDD doping profile by taking advantage of phosphorus TED.

This paper describes a leading-edge 0.18 /spl mu/m CMOS logic foundry technology. Very aggressive design rules and borderless contacts render a 4.4 /spl mu/m/sup 2/ embedded (synchronous cache) 6T SRAM cell demonstrated in a 1 Mb vehicle with very high yield. Robust dual-gate oxides were developed to support 1.5-2 V core logic as well as 3.3 V periphery (I/O) circuitry. Advanced modular core device technology using 32 /spl Aring/ oxides for 1.8-2 V operation and 27 /spl Aring/ oxides for 1.5-1.7 V applications support competitive high-performance (MPU/graphics) or low-standby power (mobile) applications. Transient-enhanced diffusion is effectively used in I/O devices to enhance hot-carrier lifetime. This is the first 0.18 /spl mu/m technology demonstrating a highly manufacturable 6 to 7 level low-k (HSQ)/AlCu interconnect system with tightest metal pitch (0.46 /spl mu/m M1 and 0.56 /spl mu/m at intermediate levels), as well as aggressive borderless and fully stacked vias without poisoning problems. AlCu/FSG and dual-damascene Cu/oxide interconnect options have also been proven with comparable SRAM yield to the AlCu/HSQ system.

This paper reports for the first time the growth of ultra- thin gate oxide by rapid thermal oxidation using in-situ generated steam (Wet RTO). Compared to conventional gate oxide grown by wet furnace and dry RTO, excellent oxide integrity of Wet RTO is demonstrated. Furthermore, the Wet RTO oxides nitrided by in-situ NO rapid thermal anneal also exhibits improved device transconductance, current drivability, and hot carrier reliability.