Logic

We demonstrate MOVPE-growth of InAs/AlAs0.16Sb0.84/GaSb and InAs/AlAs0.16Sb0.84/InAs heterostructures of excellent quality as observed by transmission electron microscopy and x-ray diffraction 2-theta-omega and rocking curve scans with full width at half maximum routinely below 100″. Key points regarding interface control for heteroepitaxial nucleation are reviewed and the choice of suitable precursors to minimize the incorporation of C and O are discussed.

The growth of heterostructures lattice matched to InAs(100) substrates for high mobility electronic devices has been investigated. The oxide removal process and homoepitaxial nucleation depends on the deposition parameters to avoid the formation of surface defects that can propagate through the structure during growth which can result in degraded device performance. The growth parameters for InAs homoepitaxy were found to be within an extremely narrow range when using As4 with a slight increase using As2. High structural quality lattice matched AlAsxSb1−x buffer layer was grown on InAs(100) substrates using a digital growth technique with the AlAs mole fraction adjusted by varying the incident As flux. Using the AlAsxSb1−x buffer layer, the transport properties of thin InAs channel layers were determined on conducting native substrates.

Narrow 〈110〉Si oriented trenches with high aspect ratio served as template to grow Ge on Si (001) substrate. Cross section high resolution transmission electron microscopy reveals a high crystalline quality relaxed Ge inside the trench with only a few structural defects in the vicinity of a well ordered misfit dislocation grid at the Ge/Si interface. These dislocations are formed along the 〈111〉Ge lattice planes and terminate in the first 20 nm of grown Ge. The high structural Ge quality is maintained both parallel and perpendicular to the trench as was confirmed by additional plan view and cross section inspections along the trench.

We report an ultrashallow metallic source/drain (S/D) contact scheme for fully self-aligned III-V NMOS with specific contact resistivity and sheet resistance which, for the first time, demonstrate performance metrics that may be compatible with the ITRS R ext requirements for 12-nm technology generation device pitch. The record specific contact resistivity between the contact pad and metallic S/D of ρ c = 2.7 ·10 -9 Ω·cm 2 has been demonstrated for 10 nm undoped InAs channels by forming an ultrashallow crystalline ternary NiInAs phase with R sh = 97 Ω/sq for a junction depth of 7 nm. The junction depth of the S/D scheme is highly controllable and atomically abrupt.

We report the first demonstration of scaled Ge p-channel FinFET devices fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [1]. Excellent subthreshold characteristics (long-channel subthreshold swing SS=76mV/dec at 0.5V), good SCE control and high transconductance (1.2 mS/μm at 1V, 1.05 mS/μm at 0.5V) are achieved. The Ge FinFET presented in this work exhibits highest g m /SS at V dd =1V reported for non-planar unstrained Ge pFETs to date.

The growth and bonding chemistry at a gate dielectric Ga2O3/GaAs interface is investigated using in-situ photoemission techniques. A multi-chamber molecular beam epitaxy/analysis system allows for the controlled deposition of III–V and oxide layers and the probing of these layers without exposure to atmosphere. The growth of Ga2O3 on a (2×4) reconstructed GaAs surface proceeds with molecules of Ga2O insertion into pairs of As-dimers with the surface void of As–O bonding. Subsequent growth involved the combination of Ga2O with oxygen to form Ga2O3. However, for stoichiometric Ga2O3, the substrate temperature >440 °C is required to provide the necessary energy for the reaction. This growth process is unique and represents a method for unpinning the Fermi level for GaAs with a low level of interface state density required for the fabrication of enhancement mode MOSFET devices.

A classification scheme for III-V MOSFETs for future CMOS is proposed and n-channel devices are benchmarked both within the group of III-V MOSFETs and in comparison with state-of-the-art silicon MOSFETs. Metrics which are based on the first derivative of drain current (I d ) vs gate voltage (V gs ) are found to be most suitable for benchmarking technologies of widely diverging maturity level. Although recently reported III-V MOSFETs exhibit markedly improved performance, they still lag state-of the-art Si MOSFETs. However, Schottky gate III-V devices with an InAs channel layer already outperform silicon MOSFETs today.

In this paper, we present an advanced integration approach using milli-second anneal technique to enhance device performance. In addition to enhanced poly-silicon activation, the device gain resulted from channel stress modulation, and retarded dopant diffusion can be obtained through process optimization including rapid-thermal anneal (RTA), capping layer, and milli-second anneal. More than 15% NMOS performance gain is demonstrated without undergoing milli-second-anneal-induced pattern loading effect and re-crystallization defect. No obvious stress relaxation and driving current degradation are observed in epi-SiGe PMOS. Moreover, the performance gain is increased while lowering the RTA temperature, suggesting that our proposed approach may open an alternative pathway for 45nm technology node and beyond

We report solutions to the formidable challenges posed by integrating a HfSiON dielectric with a poly-Si gate for low-power device technology. A 1.5 nm EOT HfSiON is demonstrated with mobility comparable to SiO/sub 2/ and 3 orders of magnitude leakage reduction. A novel boron delta-doped strained-SiGe channel points a way out of the high threshold voltage problem associated with Fermi-pinning at the high-k/poly-Si interface and ameliorates short-channel effects in PMOS devices. In addition, a 20% hole mobility enhancement and 15% I/sub on/-I/sub off/ characteristics improvement are achieved owing to the compressive SiGe channel. NMOS PBTI lifetime of 35 years, and PMOS NBTI and NMOS hot carrier lifetimes of more than 1000 years are demonstrated at 1.2 V.

Current foundry technology menus are so rich that they are sufficient to provide single chip solutions to a wide variety of desktop, portable and communication systems. At 130-nm and 90-nm generations, many of the device characteristics are no longer a straightforward extension of past generations. Special attention should be made for mixed-signal chip design. A judicious choice of devices and careful trade-off between version options should be made to maximize the benefit from the latest foundry offerings.