7nm FinFET Plasma Charge Recording Device
A new wafer-level coupling plasma charge recorder fabricated with 7nm FinFET CMOS logic process is presented in this paper. This plasma ion charge recording device provides the historic and quantitative plasma ion charges of damascene metallization steps in advanced 7nm FinFET COMS logic processes. The high-resolution plasma ion recorder is formed by an accurate FinFET coupling structure to store the plasma ion level and distribution of the whole wafer. By a simple wafer-level WAT measurement, the promising plasma charge recording device can efficiently collect the accumulated ion charges, ion polarization, and tiny plasma fluctuation of each metallization process step in 7nm FinFET CMOS logic technologies, which definitely provides a superior device and method in developing a reliable and non-latent plasma damage process for 7nm FinFET technology and beyond. authors: Yi-Pei Tsai, Jiaw-Ren Shih, Ya-Chin King, Chrong Jung Lin
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
